Patents by Inventor Brett L. Williams

Brett L. Williams has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240138971
    Abstract: Devices and methods for treatment of bodily lumens and sphincters are disclosed. Some embodiments include methods and devices for inducing an inflammatory response and development of fibrosis, collagen, and/or scar tissue. In some embodiments, scaffolds may be composed of a matrix of filaments. Application of the methods and devices disclosed herein to treat Gastroesophageal Reflux Disease (GERD) and other sphincter disorders are discussed. Biodegradable scaffolds configured to induce an inflammatory response are also disclosed.
    Type: Application
    Filed: January 4, 2024
    Publication date: May 2, 2024
    Inventors: Robert A. Ganz, Gabriel L. Ganz, Ryan Timothy Balko, Justin James Herbert, Brett Allyn Williams
  • Publication number: 20240138972
    Abstract: Devices and methods for treatment of bodily lumens and sphincters are disclosed. Some embodiments include methods and devices for inducing an inflammatory response and development of fibrosis, collagen, and/or scar tissue. In some embodiments, scaffolds may be composed of a matrix of filaments. Application of the methods and devices disclosed herein to treat Gastroesophageal Reflux Disease (GERD) and other sphincter disorders are discussed. Biodegradable scaffolds configured to induce an inflammatory response are also disclosed.
    Type: Application
    Filed: January 4, 2024
    Publication date: May 2, 2024
    Inventors: Robert A. Ganz, Gabriel L. Ganz, Ryan Timothy Balko, Justin James Herbert, Brett Allyn Williams
  • Patent number: 10355001
    Abstract: A memory system includes a memory controller and a memory module coupled to the memory controller. One such memory module may include a memory package of a first type and a signal presence detect unit configured to provide configuration data associated with a memory package of a second type to the memory controller. The configuration data may be used to configure the memory controller to interface with the memory package of a first type.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: July 16, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Brett L. Williams, Thomas H. Kinsley
  • Publication number: 20190088651
    Abstract: A memory system includes a memory controller and a memory module coupled to the memory controller. One such memory module may include a memory package of a first type and a signal presence detect unit configured to provide configuration data associated with a memory package of a second type to the memory controller. The configuration data may be used to configure the memory controller to interface with the memory package of a first type.
    Type: Application
    Filed: November 16, 2018
    Publication date: March 21, 2019
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Brett L. Williams, Thomas H. Kinsley
  • Patent number: 10141314
    Abstract: A memory system includes a memory controller and a memory module coupled to the memory controller. One such memory module may include a memory package of a first type and a signal presence detect unit configured to provide configuration data associated with a memory package of a second type to the memory controller. The configuration data may be used to configure the memory controller to interface with the memory package of a first type.
    Type: Grant
    Filed: February 15, 2012
    Date of Patent: November 27, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Brett L. Williams, Thomas H. Kinsley
  • Publication number: 20120284480
    Abstract: A memory system includes a memory controller and a memory module coupled to the memory controller. One such memory module may include a memory package of a first type and a signal presence detect unit configured to provide configuration data associated with a memory package of a second type to the memory controller. The configuration data may be used to configure the memory controller to interface with the memory package of a first type.
    Type: Application
    Filed: February 15, 2012
    Publication date: November 8, 2012
    Applicant: Micron Technology, Inc.
    Inventors: Brett L. Williams, Thomas H Kinsley
  • Patent number: 7681005
    Abstract: An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. Transitions of the Read/Write control line during a burst access will terminate the burst access, reset the burst length counter and initialize the device for another burst access. The device is compatible with existing Extended Data Out DRAM device pinouts, Fast Page Mode and Extended Data Out Single In-Line Memory Module pinouts, and other memory circuit designs.
    Type: Grant
    Filed: May 20, 1996
    Date of Patent: March 16, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Jeffrey S. Mailloux, Kevin J. Ryan, Todd A. Merritt, Brett L. Williams
  • Patent number: 7681006
    Abstract: An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. Transitions of the Read/Write control line during a burst access will terminate the burst access, reset the burst length counter and initialize the device for another burst access. The device is compatible with existing Extended Data Out DRAM device pinouts, Fast Page Mode and Extended Data Out Single In-Line Memory Module pinouts, and other memory circuit designs.
    Type: Grant
    Filed: December 3, 1997
    Date of Patent: March 16, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Jeffrey S. Mailloux, Kevin J. Ryan, Todd A. Merritt, Brett L. Williams
  • Patent number: 7124256
    Abstract: An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. Transitions of the Read/Write control line during a burst access will terminate the burst access, reset the burst length counter and initialize the device for another burst access. The device is compatible with existing Extended Data Out DRAM device pinouts, Fast Page Mode and Extended Data Out Single In-Line Memory Module pinouts, and other memory circuit designs.
    Type: Grant
    Filed: December 3, 1997
    Date of Patent: October 17, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Jeffrey S. Mailloux, Kevin J. Ryan, Todd A. Merritt, Brett L. Williams
  • Patent number: 7103742
    Abstract: An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. Transitions of the Read/Write control line during a burst access will terminate the burst access, reset the burst length counter and initialize the device for another burst access. The device is compatible with existing Extended Data Out DRAM device pinouts, Fast Page Mode and Extended Data Out Single In-Line Memory Module pinouts, and other memory circuit designs.
    Type: Grant
    Filed: December 3, 1997
    Date of Patent: September 5, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Jeffrey S. Mailloux, Kevin J. Ryan, Todd A. Merritt, Brett L. Williams
  • Patent number: 6615325
    Abstract: An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. Transitions of the Read/Write control line during a burst access will terminate the burst access, reset the burst length counter and initialize the device for another burst access. The device is compatible with existing Extended Data Out DRAM device pinouts, Fast Page Mode and Extended Data Out Single In-Line Memory Module pinouts, and other memory circuit designs.
    Type: Grant
    Filed: December 3, 1997
    Date of Patent: September 2, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Jeffrey S. Mailloux, Kevin J. Ryan, Todd A. Merritt, Brett L. Williams
  • Patent number: 6587896
    Abstract: A memory bus impedance matching module is inserted in each empty memory expansion socket on a computer memory bus to provide a constant impedance on the bus. Impedance devices, such as non-functional memory devices, are mounted on the module housing and coupled to standard bus communication line connections on the module housing. The modules are placed on the memory bus to prevent communication errors without needing to fill each expansion socket with real memory.
    Type: Grant
    Filed: February 27, 1998
    Date of Patent: July 1, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Donald Baldwin, Brett L. Williams
  • Patent number: 6584543
    Abstract: A memory structure includes a memory module divided into low order banks and high order banks. The low order banks are used as conventional memory. The high order banks are used as either conventional memory or ECC memory, depending upon routing of data. In one embodiment, data from the high order banks are routed through a primary multiplexer to a data bus when the high order banks are used as conventional memory. When the high order banks are used as ECC memory, data from the auxiliary section is routed through the primary multiplexer to an error correction circuit. A secondary multiplexer combines ECC bits from the auxiliary section of the module or a dedicated ECC memory on a motherboard. The auxiliary section thus supplements the onboard ECC memory to provide support for an effectively larger ECC memory for use with error intolerant applications that require error correction.
    Type: Grant
    Filed: November 14, 2002
    Date of Patent: June 24, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Brett L. Williams, Donald D. Baldwin
  • Publication number: 20030084233
    Abstract: A system is capable of receiving Fast Page mode, Extended Data Out mode, Burst Extended Data Out mode, or a combination of these memory devices. A method of determining the type of memory present allows the system to adjust internal memory access signals in accordance with the type of memory installed. The system may be shipped with a first type of memory, and then upgraded to a second type of memory by the user to improve overall system performance. A first bank of memory may be of a first type, and a second bank may be of another type. The user may make cost versus performance decisions when upgrading memory types or capacities.
    Type: Application
    Filed: June 1, 1995
    Publication date: May 1, 2003
    Inventor: BRETT L. WILLIAMS
  • Publication number: 20030070054
    Abstract: A memory structure includes a memory module divided into low order banks and high order banks. The low order banks are used as conventional memory. The high order banks are used as either conventional memory or ECC memory, depending upon routing of data. In one embodiment, data from the high order banks are routed through a primary multiplexer to a data bus when the high order banks are used as conventional memory. When the high order banks are used as ECC memory, data from the auxiliary section is routed through the primary multiplexer to an error correction circuit. A secondary multiplexer combines ECC bits from the auxiliary section of the module or a dedicated ECC memory on a motherboard. The auxiliary section thus supplements the onboard ECC memory to provide support for an effectively larger ECC memory for use with error intolerant applications that require error correction.
    Type: Application
    Filed: November 14, 2002
    Publication date: April 10, 2003
    Inventors: Brett L. Williams, Donald D. Baldwin
  • Publication number: 20020133665
    Abstract: An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. Transitions of the Read/Write control line during a burst access will terminate the burst access, reset the burst length counter and initialize the device for another burst access. The device is compatible with existing Extended Data Out DRAM device pinouts, Fast Page Mode and Extended Data Out Single In-Line Memory Module pinouts, and other memory circuit designs.
    Type: Application
    Filed: December 3, 1997
    Publication date: September 19, 2002
    Inventors: JEFFREY S. MAILLOUX, KEVIN J. RYAN, TODD A. MERRITT, BRETT L. WILLIAMS
  • Patent number: 6397290
    Abstract: A memory structure includes a memory module divided into low order banks and high order banks. The low order banks are used as conventional memory. The high order banks are used as either conventional memory or ECC memory, depending upon routing of data. In one embodiment, data from the high order banks are routed through a primary multiplexer to a data bus when the high order banks are used as conventional memory. When the high order banks are used as ECC memory, data from the auxiliary section is routed through the primary multiplexer to an error correction circuit. A secondary multiplexer combines ECC bits from the auxiliary section of the module or a dedicated ECC memory on a motherboard. The auxiliary section thus supplements the onboard ECC memory to provide support for an effectively larger ECC memory for use with error intolerant applications that require error correction.
    Type: Grant
    Filed: August 17, 2001
    Date of Patent: May 28, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Brett L. Williams, Donald D. Baldwin
  • Publication number: 20020029316
    Abstract: A memory structure includes a memory module divided into low order banks and high order banks. The low order banks are used as conventional memory. The high order banks are used as either conventional memory or ECC memory, depending upon routing of data. In one embodiment, data from the high order banks are routed through a primary multiplexer to a data bus when the high order banks are used as conventional memory. When the high order banks are used as ECC memory, data from the auxiliary section is routed through the primary multiplexer to an error correction circuit. A secondary multiplexer combines ECC bits from the auxiliary section of the module or a dedicated ECC memory on a motherboard. The auxiliary section thus supplements the onboard ECC memory to provide support for an effectively larger ECC memory for use with error intolerant applications that require error correction.
    Type: Application
    Filed: August 17, 2001
    Publication date: March 7, 2002
    Inventors: Brett L. Williams, Donald D. Baldwin
  • Publication number: 20020029315
    Abstract: A memory structure includes a memory module divided into low order banks and high order banks. The low order banks are used as conventional memory. The high order banks are used as either conventional memory or ECC memory, depending upon routing of data. In one embodiment, data from the high order banks are routed through a primary multiplexer to a data bus when the high order banks are used as conventional memory. When the high order banks are used as ECC memory, data from the auxiliary section is routed through the primary multiplexer to an error correction circuit. A secondary multiplexer combines ECC bits from the auxiliary section of the module or a dedicated ECC memory on a motherboard. The auxiliary section thus supplements the onboard ECC memory to provide support for an effectively larger ECC memory for use with error intolerant applications that require error correction.
    Type: Application
    Filed: August 10, 2001
    Publication date: March 7, 2002
    Inventors: Brett L. Williams, Donald D. Baldwin
  • Publication number: 20010044875
    Abstract: An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. Transitions of the Read/Write control line during a burst access will terminate the burst access, reset the burst length counter and initialize the device for another burst access. The device is compatible with existing Extended Data Out DRAM device pinouts, Fast Page Mode and Extended Data Out Single In-Line Memory Module pinouts, and other memory circuit designs.
    Type: Application
    Filed: December 3, 1997
    Publication date: November 22, 2001
    Inventors: JEFFREY S. MAILLOUX, KEVIN J. RYAN, TOBB A. MERRITT, BRETT L. WILLIAMS