Abstract: Capacitive coupling between adjacent parallel lines in an integrated circuit is made more uniform and allows for better timing control of the lines through the use of inverters placed on one or both of the adjacent interconnect lines. By staggering the placement of inverters along adjacent lines, constructive and destructive coupling terms between the lines are balanced out. The propagation delay through the inverter is made less than the propagation delay through one half of the line length of the corresponding line.

Abstract: An integrated circuit memory architecture with selectively offset data and address delays to minimize skew and provide synchronization of signals at the input/output section in which the architecture is divided into memory sections, depending upon their distance from the address/control generation block. The address and clock information is re-driven between these sections, which effectively serves to add a quantized number of gate delays in the address path between the sections while concomitantly minimizing skew. A corresponding number of gate delays is also added to the “read” data path for each section such that the number of delays in the address/clock path plus the number of delays in the “read” data path is substantially constant.

Abstract: An integrated circuit memory architecture with selectively offset data and address delays to minimize skew and provide synchronization of signals at the input/output section in which the architecture is divided into memory sections, depending upon their distance from the address/control generation block. The address and clock information is re-driven between these sections, which effectively serves to add a quantized number of gate delays in the address path between the sections while concomitantly minimizing skew. A corresponding number of gate delays is also added to the “read” data path for each section such that the number of delays in the address/clock path plus the number of delays in the “read” data path is substantially constant.

Abstract: A pre-biased voltage level shifting circuit of especial applicability with respect to those integrated circuit devices requiring a technique for converting circuit operation between differing power supply levels. In a representative embodiment, the circuit utilizes feedback to make the switching transistors faster to thereby increase the speed of the level translation of signals based upon two different power supplies.

Abstract: A pre-biased voltage level shifting circuit of especial applicability with respect to those integrated circuit devices requiring a technique for converting circuit operation between differing power supply levels. In a representative embodiment, the circuit utilizes feedback to make the switching transistors faster to thereby increase the speeds of the level translation of signals based upon two different power supplies.

Abstract: A high speed output enable path and method for an integrated circuit device which effectively minimizes the gate delays in the critical integrated circuit device data and clock paths and in which most amplification is added in the reset path which is not critical to access time. Based on an external clock, several “one-shot” internal output enable clocks are generated. These parallel output enable clocks have select information embedded in them to facilitate the multiplexing of several different data paths onto a single output buffer. This select information is implemented ir the reset portion of the one-shot circuit thereby removing it from the critical portion for determining access time.

Abstract: A current sensing differential amplifier with high rejection of power supply variations and method for an integrated circuit memory device which allows the amplifier's differential voltage level and speed to track that of the sense amplifier supplying the information, thereby achieving the needed margin for critical synchronous timing. The reliability of the differential amplifier is also increased due to the provision of a larger differential signal and higher supply voltage levels. In a preferred embodiment, an n-channel transistor serves as a regulator with its drain terminal coupled to an unregulated supply voltage source ("V.sub.cc "). The gate of the transistor is then coupled to a regulated supply voltage ("V.sub.ccp ") which is a function of the voltage supply for the sense amplifier. The source of the transistor is connected to the sources of the p-channel transistors in the main amplifier which provide feedback to the main amplifier.

Abstract: A reference cell for a 1T-1C memory is disclosed for use in either an open or folded memory cell array. Each reference cell has two outputs each coupled to a bit line that each develop a voltage substantially half of that developed by a ferroelectric memory cell. The reference voltages and memory cell voltage are than resolved by a sense amplifier. Each reference cell includes two ferroelectric capacitors that are the same size and fabricated with the identical process as the memory cell ferroelectric capacitors. Any changes in the memory cell capacitor similarly affects the reference cell capacitor, and thus the reference voltage is always substantially half of that developed by the memory cell. The reference cells include a number of timing inputs, which control charge sharing and configure the cell to operate in either a DRAM or FRAM.RTM. mode. In a first embodiment, one of the reference cell capacitors is poled.

Abstract: A reference cell for a IT-1C memory can be used in either an open or folded memory cell array. Each reference cell has two outputs each coupled to a bit line that each develop a voltage substantially half of that developed by a ferroelectric memory cell. The reference voltages and memory cell voltage are than resolved by a sense amplifier. Each reference cell includes two ferroelectric capacitors that are the same size and fabricated with the identical process as the memory cell ferroelectric capacitors. Any changes in the memory cell capacitor similarly affects the reference cell capacitor, and thus the reference voltage is always substantially half of that developed by the memory cell. The reference cells include a number of timing inputs, which control charge sharing and configure the cell to operate in either a DRAM or FRAM.RTM. mode. In a first embodiment, one of the reference cell capacitors is poled.

Abstract: A ferroelectric memory includes a bit line for developing a signal coupled to a ferroelectric memory cell. An integrated load capacitor and sense amplifier are also coupled to the bit line. An isolation circuit is included for selectively electrically isolating the bit line load capacitor from the sense amplifier and ferroelectric memory cell during the active operation of the sense amplifier. The isolation circuit is compatible with both non-volatile ferroelectric and volatile dynamic memory operation.