Patents by Inventor Brett Sawyer
Brett Sawyer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11923327Abstract: A silicon integrated circuit. In some embodiments, the silicon integrated circuit includes a first conductive trace, on a top surface of the silicon integrated circuit, a dielectric layer, on the first conductive trace, and a second conductive trace, on the dielectric layer, connected to the first conductive trace through a first via.Type: GrantFiled: June 5, 2020Date of Patent: March 5, 2024Assignee: Rockley Photonics LimitedInventors: Michael Lee, John Paul Drake, Ying Luo, Vivek Raghunathan, Brett Sawyer
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Publication number: 20230343686Abstract: A semiconductor package. In some embodiments, the package has a top surface and a bottom surface, and includes: a semiconductor die having a front surface, a back surface, and a plurality of edges; a mold compound, on the back surface of the die and the edges of the die; a plurality of first conductive elements extending through the mold compound on the back surface of the die to the top surface of the package; and a plurality of second conductive elements on the bottom surface of the package.Type: ApplicationFiled: December 14, 2020Publication date: October 26, 2023Inventors: SEUNGJAE LEE, Brett SAWYER, David Arlo NELSON
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Publication number: 20230089415Abstract: An integrated switch assembly having a stacked configuration, the integrated switch assembly comprising: a first layer, the first layer comprising a photonic integrated circuit, PIC; a second layer, the second layer comprising a switch ASIC; wherein the first layer is mounted onto a substrate and the second layer is mounted on top of the first layer.Type: ApplicationFiled: March 5, 2021Publication date: March 23, 2023Inventors: Aaron John ZILKIE, Guomin YU, Brett SAWYER
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Patent number: 11573387Abstract: An optical engine. In some embodiments, the optical engine includes an electronic interfacing component including: an upper surface having a plurality of conductors for forming a corresponding plurality of connections to a host board, a lower surface having a plurality of conductors for forming a corresponding plurality of connections to one or more optoelectronic elements, and a plurality of vias extending from the lower surface to the upper surface.Type: GrantFiled: March 31, 2020Date of Patent: February 7, 2023Inventors: Brett Sawyer, Seungjae Lee, Chia-Te Chou, Vivek Raghunathan, Vivek Raghuraman, Karlheinz Muth, David Arlo Nelson
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Publication number: 20220336433Abstract: A siliconized heterogeneous optical engine. In some embodiments, the siliconized heterogeneous optical engine includes a photonic integrated circuit; an electro-optical chip, on a top surface of the photonic integrated circuit; an electronic integrated circuit, on the top surface of the photonic integrated circuit; an interposer, on the top surface of the photonic integrated circuit; a redistribution layer, on a top surface of the interposer, the redistribution layer including a plurality of conductive traces; and a plurality of protruding conductors, on the conductive traces of the redistribution layer. The electronic integrated circuit may be electrically connected to the electro-optical chip and to a conductive trace of the plurality of conductive traces of the redistribution layer.Type: ApplicationFiled: September 11, 2020Publication date: October 20, 2022Inventors: SEUNGJAE LEE, Chia-Te CHOU, Vivek RAGUNATHAN, Brett SAWYER
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Publication number: 20220319971Abstract: A via frame. In some embodiments, the via frame includes: a sheet of epoxy mold compound, having a plurality of holes each extending through the sheet of epoxy mold compound, and a plurality of conductive elements, each extending through a respective one of the holes.Type: ApplicationFiled: July 10, 2020Publication date: October 6, 2022Inventors: SEUNGJAE LEE, Brett SAWYER, Gerald Cois BYRD
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Publication number: 20220310540Abstract: A silicon integrated circuit. In some embodiments, the silicon integrated circuit includes a first conductive trace, on a top surface of the silicon integrated circuit, a dielectric layer, on the first conductive trace, and a second conductive trace, on the dielectric layer, connected to the first conductive trace through a first via.Type: ApplicationFiled: June 5, 2020Publication date: September 29, 2022Inventors: Michael LEE, John Paul DRAKE, Ying LUO, Vivek RAGHUNATHAN, Brett SAWYER
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Patent number: 11387186Abstract: A system integrating a fan-out package, including a first semiconductor die, with a second semiconductor die. In some embodiments the fan-out package includes the first semiconductor die, a mold compound, covering the first semiconductor die on at least two sides, and an electrical contact, on a lower surface of the first semiconductor die. The fan-out package may have a rabbet along a portion of a lower edge of the fan-out package.Type: GrantFiled: November 20, 2019Date of Patent: July 12, 2022Assignee: Rockley Photonics LimitedInventors: Seungjae Lee, Brett Sawyer, Chia-Te Chou
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Patent number: 11342270Abstract: A system integrating a fan-out package, including a first semiconductor die, with a second semiconductor die. In some embodiments the fan-out package includes the first semiconductor die, a mold compound, covering the first semiconductor die on at least two sides, and an electrical contact, on a lower surface of the first semiconductor die. The fan-out package may have a rabbet along a portion of a lower edge of the fan-out package.Type: GrantFiled: November 20, 2019Date of Patent: May 24, 2022Assignee: Rockley Photonics LimitedInventors: Seungjae Lee, Brett Sawyer, Chia-Te Chou
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Publication number: 20220122924Abstract: An assembly. In some embodiments, the assembly includes a first semiconductor chip, a substrate, and a first alignment element. The alignment of the first semiconductor chip and the substrate may be determined at least in part by engagement of the first alignment element with a first recessed alignment feature, in a surface of the first semiconductor chip.Type: ApplicationFiled: October 18, 2021Publication date: April 21, 2022Inventors: Chia-Te CHOU, Brett SAWYER, David MCCANN
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Publication number: 20220021179Abstract: Embodiments are directed to a photonic device that includes a first substrate defining a surface and a trench forming a depression along a portion of the surface, and a second substrate coupled with the surface and extending from the surface to form a raised portion around the trench. The photonic device can also include a laser die positioned within the trench, such that the laser die is surrounded by the second substrate, and an optical material positioned within a region between the laser die and the second substrate. The photonic device can further include a third substrate coupled with the second substrate such that the second substrate is positioned between the first substrate and the third substrate such that the second substrate is configured to at least partially isolate the laser die from mechanical stress exerted on the optical device.Type: ApplicationFiled: July 19, 2021Publication date: January 20, 2022Inventors: SeungJae Lee, Brett Sawyer, Chia-Te Chou, Jerry Byrd, Hooman Abediasl
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Patent number: 11054597Abstract: An electro-optical package. In some embodiments, the electro-optical package includes a first electro-optical chip coupled to an array of optical fibers, and a first physical medium dependent integrated circuit coupled to the first electro-optical chip.Type: GrantFiled: April 11, 2019Date of Patent: July 6, 2021Assignee: Rockley Photonics LimitedInventors: Vivek Raghunathan, Vivek Raghuraman, Karlheinz Muth, David Arlo Nelson, Chia-Te Chou, Brett Sawyer, SeungJae Lee
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Patent number: 10962728Abstract: An assembly. In some embodiments, the assembly includes: a photonic integrated circuit; and an electronic integrated circuit. A front surface of the photonic integrated circuit abuts, in an area of overlap, against a front surface of the electronic integrated circuit. A first portion of the photonic integrated circuit overhangs a first edge of the electronic integrated circuit, and a first portion of the electronic integrated circuit overhangs a first edge of the photonic integrated circuit. A conductor on the front surface of the electronic integrated circuit is connected, in the area of overlap, to a conductor on the front surface of the photonic integrated circuit.Type: GrantFiled: March 19, 2020Date of Patent: March 30, 2021Assignee: Rockley Photonics LimitedInventors: David Arlo Nelson, Seungjae Lee, Brett Sawyer
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Patent number: 10921538Abstract: An electro-optical package. In some embodiments, the electro-optical package includes a first electro-optical chip coupled to an array of optical fibers, and a first physical medium dependent integrated circuit coupled to the first electro-optical chip.Type: GrantFiled: April 11, 2019Date of Patent: February 16, 2021Assignee: Rockley Photonics LimitedInventors: Vivek Raghunathan, Vivek Raghuraman, Karlheinz Muth, David Arlo Nelson, Chia-Te Chou, Brett Sawyer, SeungJae Lee
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Publication number: 20200225430Abstract: An optical engine. In some embodiments, the optical engine includes an electronic interfacing component including: an upper surface having a plurality of conductors for forming a corresponding plurality of connections to a host board, a lower surface having a plurality of conductors for forming a corresponding plurality of connections to one or more optoelectronic elements, and a plurality of vias extending from the lower surface to the upper surface.Type: ApplicationFiled: March 31, 2020Publication date: July 16, 2020Inventors: Brett Sawyer, SEUNGJAE LEE, Chia-Te Chou, Vivek Raghunathan, Vivek Raghuraman, Karlheinz Muth, David Arlo Nelson
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Publication number: 20200219865Abstract: An assembly. In some embodiments, the assembly includes: a photonic integrated circuit; and an electronic integrated circuit. A front surface of the photonic integrated circuit abuts, in an area of overlap, against a front surface of the electronic integrated circuit. A first portion of the photonic integrated circuit overhangs a first edge of the electronic integrated circuit, and a first portion of the electronic integrated circuit overhangs a first edge of the photonic integrated circuit. A conductor on the front surface of the electronic integrated circuit is connected, in the area of overlap, to a conductor on the front surface of the photonic integrated circuit.Type: ApplicationFiled: March 19, 2020Publication date: July 9, 2020Inventors: David Arlo Nelson, SEUNGJAE LEE, Brett Sawyer
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Publication number: 20200161243Abstract: A system integrating a fan-out package, including a first semiconductor die, with a second semiconductor die. In some embodiments the fan-out package includes the first semiconductor die, a mold compound, covering the first semiconductor die on at least two sides, and an electrical contact, on a lower surface of the first semiconductor die. The fan-out package may have a rabbet along a portion of a lower edge of the fan-out package.Type: ApplicationFiled: November 20, 2019Publication date: May 21, 2020Inventors: SEUNGJAE LEE, Brett Sawyer, Chia-Te Chou
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Publication number: 20190317287Abstract: An electro-optical package. In some embodiments, the electro-optical package includes a first electro-optical chip coupled to an array of optical fibers, and a first physical medium dependent integrated circuit coupled to the first electro-optical chip.Type: ApplicationFiled: April 11, 2019Publication date: October 17, 2019Inventors: Vivek Raghunathan, Vivek Raghuraman, Karlheinz Muth, David Arlo Nelson, Chia-Te Chou, Brett Sawyer, SeungJae Lee