Abstract: A method and apparatus for implementing integrated circuit security features are provided to selectively disable testability features on an integrated circuit chip. A test disable logic circuit receives a test enable signal and responsive to the test enable signal set for a test mode, establishes a test mode and disables ASIC signals. Responsive to the test enable signal not being set, the ASIC signals are enabled for a functional mode and the testability features on the integrated circuit chip are disabled. When the functional mode is enabled, the test disable logic circuit prevents the test mode from being established while the integrated circuit chip is powered up.

Abstract: A method and apparatus implement balanced clock distribution networks on application specific integrated circuits (ASICs) with voltage islands functioning at multiple operating points of voltage and temperature, and a design structure on which the subject circuit resides is provided. A clock source is coupled to an N-level balanced clock tree providing a clock signal. Each of a plurality of voltage islands includes a respective voltage shifter and programmable delay function receiving the clock signal. Each respective voltage shifter and programmable delay function provides a second clock signal to a respective balanced clock tree for the associated voltage island. A system controller provides a respective control input to each respective voltage shifter and programmable delay function. The respective control input is varied dynamically corresponding to an operational mode of the respective voltage island.

Abstract: A method and apparatus for implementing integrated circuit security features are provided to selectively disable testability features on an integrated circuit chip. A test disable logic circuit receives a test enable signal and responsive to the test enable signal set for a test mode, establishes a test mode and disables ASIC signals. Responsive to the test enable signal not being set, the ASIC signals are enabled for a functional mode and the testability features on the integrated circuit chip are disabled. When the functional mode is enabled, the test disable logic circuit prevents the test mode from being established while the integrated circuit chip is powered up.

Abstract: A method and apparatus implement balanced clock distribution networks on application specific integrated circuits (ASICs) with voltage islands functioning at multiple operating points of voltage and temperature, and a design structure on which the subject circuit resides is provided. A clock source is coupled to an N-level balanced clock tree providing a clock signal. Each of a plurality of voltage islands includes a respective voltage shifter and programmable delay function receiving the clock signal. Each respective voltage shifter and programmable delay function provides a second clock signal to a respective balanced clock tree for the associated voltage island. A system controller provides a respective control input to each respective voltage shifter and programmable delay function. The respective control input is varied dynamically corresponding to an operational mode of the respective voltage island.

Abstract: A method, apparatus and computer program product are provided for implementing enhanced notification and control features in an oscilloscope. User selected notification options and user selected control options are stored. When a predefined event is identified, the user selected notification options are used for notifying a remote user of the identified predefined event. The user selected control options are used for receiving user selections enabling the user to remotely control oscilloscope operational settings. The user can be notified with a telephone call, an email or a pager text message and the user can change operational settings using a telephone call or an email containing commands.

Abstract: A frequency shift detection circuit for detecting a frequency shift between a first signal and a second signal includes two or more delay circuits coupled to one another in series and two or more comparison logic circuits. The first delay circuit in the series receives one of the first and second signals and produces a delayed replica. Each of the other delay circuits receives the delayed replica produced by the previous delay circuit in the series and produces a further delayed replica. Thus, the signal produced by each delay circuit is delayed from the original signal by a different amount. Each comparison logic circuit receives one of the delayed replicas and receives the other one of the first and second signals, i.e., the one that is not received by the delay circuits. In response, the comparison logic circuit produces a frequency shift detection signal when it detects a phase difference between that other one of said first and second signals and the delayed replica.

Abstract: A method for removing an external frequency divider and clock formation circuit from a feedback path of a phase locked loop and a phase selector circuit are provided for synchronizing an external frequency divider with a reference clock of a phase locked loop. A reference clock signal is applied to the phase locked loop. An output of the phase locked loop is coupled through a predefined delay and provides a delayed feedback clock signal input to the phase locked loop. The external frequency divider is located at the output of the phase locked loop external to the predefined delay and outside the feedback clock signal path of the phase locked loop. A phase selector circuit identifies a correct phase of the reference clock signal and starts the external frequency divider. The phase selector circuit includes an edge detector, a synchronization divider, and a reset machine.

Abstract: A method for setting a locking frequency operating range of the phase locked loop (PLL) circuit and a phase locked loop (PLL) circuit are provided with range select logic for detecting an unknown reference clock frequency and for setting a locking frequency operating range of the phase locked loop. First a bypass mode for the phase locked loop (PLL) circuit is set. An unknown reference clock frequency is applied to a first counter. A known oscillator clock frequency is applied to a second counter. The first and second counters are reset and a timeout value of the second counter is identified. A first counter count value is compared with precalculated constant values. A set of range bits are latched responsive to said compared values. Two consecutive sets of latched range bits are compared and the steps repeated until a match of two consecutive sets of latched range bits is identified. The matching latched range bits are applied to a programmable range select input of the phase locked loop (PLL) circuit.