Patents by Inventor Brian Anthony Rinaldi
Brian Anthony Rinaldi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11822482Abstract: Provided are a computer program product for managing tracks in a storage in a cache. An active track data structure indicates tracks in the cache that have an active status. An active bit in a cache control block for a track is set to indicate active for the track indicated as active in the active track data structure. In response to processing the cache control block, a determination is made, from the cache control block for the track, whether the track is active or inactive to determine processing for the cache control block.Type: GrantFiled: November 10, 2022Date of Patent: November 21, 2023Inventors: Lokesh Mohan Gupta, Kyler A. Anderson, Kevin J. Ash, Matthew J. Kalos, Brian Anthony Rinaldi, Beth Ann Peterson, Matthew G. Borlick
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Publication number: 20230075922Abstract: Provided are a computer program product for managing tracks in a storage in a cache. An active track data structure indicates tracks in the cache that have an active status. An active bit in a cache control block for a track is set to indicate active for the track indicated as active in the active track data structure. In response to processing the cache control block, a determination is made, from the cache control block for the track, whether the track is active or inactive to determine processing for the cache control block.Type: ApplicationFiled: November 10, 2022Publication date: March 9, 2023Inventors: Lokesh Mohan Gupta, Kyler A. Anderson, Kevin J. Ash, Matthew J. Kalos, Brian Anthony Rinaldi, Beth Ann Peterson, Matthew G. Borlick
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Publication number: 20230036755Abstract: Provided are a computer program product for managing tracks in a storage in a cache. An active track data structure indicates tracks in the cache that have an active status. An active bit in a cache control block for a track is set to indicate active for the track indicated as active in the active track data structure. In response to processing the cache control block, a determination is made, from the cache control block for the track, whether the track is active or inactive to determine processing for the cache control block.Type: ApplicationFiled: July 29, 2021Publication date: February 2, 2023Inventors: Lokesh Mohan Gupta, Kyler A. Anderson, Kevin J. Ash, Matthew J. Kalos, Brian Anthony Rinaldi, Beth Ann Peterson, Matthew G. Borlick
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Patent number: 11550726Abstract: Provided are a computer program product for managing tracks in a storage in a cache. An active track data structure indicates tracks in the cache that have an active status. An active bit in a cache control block for a track is set to indicate active for the track indicated as active in the active track data structure. In response to processing the cache control block, a determination is made, from the cache control block for the track, whether the track is active or inactive to determine processing for the cache control block.Type: GrantFiled: July 29, 2021Date of Patent: January 10, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lokesh Mohan Gupta, Kyler A. Anderson, Kevin J. Ash, Matthew J. Kalos, Brian Anthony Rinaldi, Beth Ann Peterson, Matthew G. Borlick
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Patent number: 11467772Abstract: A method for improving destage performance to a RAID array is disclosed. In one embodiment, such a method periodically scans a cache for first strides that are ready to be destaged to a RAID array. While scanning the cache, the method identifies second strides that are not currently ready to be destaged to the RAID array, but will likely be ready to be destaged during a subsequent scan of the cache. The method initiates preemptive staging of any missing data of the second strides from the RAID array into the cache in preparation for the subsequent scan. Upon occurrence of the subsequent scan, the method destages, from the cache, the second strides from the cache to the RAID array. A corresponding system and computer program product are also disclosed.Type: GrantFiled: April 22, 2020Date of Patent: October 11, 2022Assignee: International Business Machines CorporationInventors: Lokesh Mohan Gupta, Clint A. Hardy, Brian Anthony Rinaldi, Karl Allen Nielsen
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Patent number: 11423158Abstract: Dynamic compression with dynamic multi-stage encryption for a data storage system in accordance with the present description includes, in one aspect of the present description, preserves end-to-end encryption between a host and a storage controller while compressing data which was received from the host in encrypted but uncompressed form, using MIPs and other processing resources of the storage controller instead of the host. In one embodiment, the storage controller decrypts encrypted but uncompressed data received from the host to unencrypted data and compresses the unencrypted data to compressed data. The storage controller then encrypts the compressed data to encrypted, compressed data and stores the encrypted, compressed data in a storage device controlled by the storage controller. Other aspects and advantages may be realized, depending upon the particular application.Type: GrantFiled: September 12, 2019Date of Patent: August 23, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Matthew G. Borlick, Alistair Leask Symon, Micah Robison, Brian Anthony Rinaldi, Lokesh M. Gupta, Mark Elliott Hack
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Patent number: 11354208Abstract: A first non-volatile dual in-line memory module (NVDIMM) of a first server and a second NVDIMM of a second server are armed during initial program load in a dual-server based storage system to configure the first NVDIMM and the second NVDIMM to retain data on power loss. Prior to initiating a safe data commit scan to destage modified data from the first server to a secondary storage, a determination is made as to whether the first NVDIMM is armed. In response to determining that the first NVDIMM is not armed, a failover is initiated to the second server.Type: GrantFiled: September 11, 2019Date of Patent: June 7, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Matthew G. Borlick, Sean Patrick Riley, Brian Anthony Rinaldi, Trung N. Nguyen, Lokesh M. Gupta
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Patent number: 11321123Abstract: Provided are a computer program product, system, and method for determining an optimum number of threads to make available per core in a multi-core processor complex to execute tasks. A determination is made of a first processing measurement based on threads executing on the cores of the processor chip, wherein each core includes circuitry to independently execute a plurality of threads. A determination is made of a number of threads to execute on the cores based on the first processing measurement. A determination is made of a second processing measurement based on the threads executing on the cores of the processor chip. A determination is made of an adjustment to the determined number of threads to execute based on the second processing measurement resulting in an adjusted number of threads. The adjusted number of threads on the cores is utilized to execute instructions.Type: GrantFiled: November 21, 2019Date of Patent: May 3, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brian Anthony Rinaldi, Lokesh M. Gupta, Kevin J. Ash, Matthew J. Kalos, Trung N. Nguyen, Clint A. Hardy, Louis A. Rasor
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Patent number: 11231855Abstract: A storage controller is configured to perform a full stride destage, a strip destage, and an individual track destage. A machine learning module receives a plurality of inputs corresponding to a plurality of factors that affect performance of data transfer operations and preservation of drive life in the storage controller. In response to receiving the inputs, the machine learning module generates a first output, a second output, and a third output that indicate a preference measure for the full stride destage, the strip destage, and the individual track destage respectively.Type: GrantFiled: April 14, 2020Date of Patent: January 25, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lokesh Mohan Gupta, Clint A. Hardy, Karl Allen Nielsen, Brian Anthony Rinaldi
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Patent number: 11226744Abstract: A first score corresponding to a full stride destage, a second score corresponding to a strip destage, and a third score corresponding to an individual track destage are computed, wherein the first score, the second score, and the third score are computed for a group of Input/Output (I/O) operations based on a first metric and a second metric, wherein the first metric is configured to affect a performance of data transfers, and wherein the second metric is configured to affect a drive life. A determination is made of a type of destage to perform based on the first score, the second score, and the third score.Type: GrantFiled: April 14, 2020Date of Patent: January 18, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Clint A. Hardy, Lokesh Mohan Gupta, Karl Allen Nielsen, Brian Anthony Rinaldi
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Publication number: 20210334038Abstract: A method for improving destage performance to a RAID array is disclosed. In one embodiment, such a method periodically scans a cache for first strides that are ready to be destaged to a RAID array. While scanning the cache, the method identifies second strides that are not currently ready to be destaged to the RAID array, but will likely be ready to be destaged during a subsequent scan of the cache. The method initiates preemptive staging of any missing data of the second strides from the RAID array into the cache in preparation for the subsequent scan. Upon occurrence of the subsequent scan, the method destages, from the cache, the second strides from the cache to the RAID array. A corresponding system and computer program product are also disclosed.Type: ApplicationFiled: April 22, 2020Publication date: October 28, 2021Applicant: International Business Machines CorporationInventors: Lokesh Mohan Gupta, Clint A. Hardy, Brian Anthony Rinaldi, Karl Allen Nielsen
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Publication number: 20210334036Abstract: In one aspect of multi-mode address mapping management in accordance with the present disclosure, mapping and unmapping operations may be conducted in one of multiple address mapping management modes to both improve overall system performance and maintain data integrity. In one embodiment, a first address mapping management mode such as a rigorous mode, for example, confirms completion of an unmapping of an address mapped data unit buffer before a re-mapping is permitted. Mapping and unmapping operations may be switched to a performance mode in which unmap completion confirmation is bypassed to improve performance. In one embodiment, address mapping management modes may be switched in real time as a function of monitored operating conditions. Other aspects and advantages are provided, depending upon the particular application.Type: ApplicationFiled: April 24, 2020Publication date: October 28, 2021Inventors: Trung N. Nguyen, Kevin J. Ash, Brian Anthony Rinaldi, Lokesh Mohan Gupta, Kyler A. Anderson
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Patent number: 11157199Abstract: In one aspect of multi-mode address mapping management in accordance with the present disclosure, mapping and unmapping operations may be conducted in one of multiple address mapping management modes to both improve overall system performance and maintain data integrity. In one embodiment, a first address mapping management mode such as a rigorous mode, for example, confirms completion of an unmapping of an address mapped data unit buffer before a re-mapping is permitted. Mapping and unmapping operations may be switched to a performance mode in which unmap completion confirmation is bypassed to improve performance. In one embodiment, address mapping management modes may be switched in real time as a function of monitored operating conditions. Other aspects and advantages are provided, depending upon the particular application.Type: GrantFiled: April 24, 2020Date of Patent: October 26, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Trung N. Nguyen, Kevin J. Ash, Brian Anthony Rinaldi, Lokesh Mohan Gupta, Kyler A. Anderson
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Publication number: 20210318806Abstract: A first score corresponding to a full stride destage, a second score corresponding to a strip destage, and a third score corresponding to an individual track destage are computed, wherein the first score, the second score, and the third score are computed for a group of Input/Output (I/O) operations based on a first metric and a second metric, wherein the first metric is configured to affect a performance of data transfers, and wherein the second metric is configured to affect a drive life. A determination is made of a type of destage to perform based on the first score, the second score, and the third score.Type: ApplicationFiled: April 14, 2020Publication date: October 14, 2021Inventors: Clint A. Hardy, Lokesh Mohan Gupta, Karl Allen Nielsen, Brian Anthony Rinaldi
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Publication number: 20210318807Abstract: A storage controller is configured to perform a full stride destage, a strip destage, and an individual track destage. A machine learning module receives a plurality of inputs corresponding to a plurality of factors that affect performance of data transfer operations and preservation of drive life in the storage controller. In response to receiving the inputs, the machine learning module generates a first output, a second output, and a third output that indicate a preference measure for the full stride destage, the strip destage, and the individual track destage respectively.Type: ApplicationFiled: April 14, 2020Publication date: October 14, 2021Inventors: Lokesh Mohan Gupta, Clint A. Hardy, Karl Allen Nielsen, Brian Anthony Rinaldi
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Publication number: 20210157635Abstract: Provided are a computer program product, system, and method for determining an optimum number of threads to make available per core in a multi-core processor complex to execute tasks. A determination is made of a first processing measurement based on threads executing on the cores of the processor chip, wherein each core includes circuitry to independently execute a plurality of threads. A determination is made of a number of threads to execute on the cores based on the first processing measurement. A determination is made of a second processing measurement based on the threads executing on the cores of the processor chip. A determination is made of an adjustment to the determined number of threads to execute based on the second processing measurement resulting in an adjusted number of threads. The adjusted number of threads on the cores is utilized to execute instructions.Type: ApplicationFiled: November 21, 2019Publication date: May 27, 2021Inventors: Brian Anthony Rinaldi, Lokesh M. Gupta, Kevin J. Ash, Matthew J. Kalos, Trung N. Nguyen, Clint A. Hardy, Louis A. Rasor
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Publication number: 20210081544Abstract: Dynamic compression with dynamic multi-stage encryption for a data storage system in accordance with the present description includes, in one aspect of the present description, preserves end-to-end encryption between a host and a storage controller while compressing data which was received from the host in encrypted but uncompressed form, using MIPs and other processing resources of the storage controller instead of the host. In one embodiment, the storage controller decrypts encrypted but uncompressed data received from the host to unencrypted data and compresses the unencrypted data to compressed data. The storage controller then encrypts the compressed data to encrypted, compressed data and stores the encrypted, compressed data in a storage device controlled by the storage controller. Other aspects and advantages may be realized, depending upon the particular application.Type: ApplicationFiled: September 12, 2019Publication date: March 18, 2021Inventors: Matthew G. Borlick, Alistair Leask Symon, Micah Robison, Brian Anthony Rinaldi, Lokesh M. Gupta, Mark Elliott Hack
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Publication number: 20210073090Abstract: A first non-volatile dual in-line memory module (NVDIMM) of a first server and a second NVDIMM of a second server are armed during initial program load in a dual-server based storage system to configure the first NVDIMM and the second NVDIMM to retain data on power loss. Prior to initiating a safe data commit scan to destage modified data from the first server to a secondary storage, a determination is made as to whether the first NVDIMM is armed. In response to determining that the first NVDIMM is not armed, a failover is initiated to the second server.Type: ApplicationFiled: September 11, 2019Publication date: March 11, 2021Inventors: Matthew G. Borlick, Sean Patrick Riley, Brian Anthony Rinaldi, Trung N. Nguyen, Lokesh M. Gupta
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Patent number: 7904752Abstract: Provided are a method, system, and article of manufacture for synchronizing device error information among nodes. A first node performs an action with respect to a first node error counter for a device in communication with the first node and a second node. The first node transmits a message to the second node indicating the device and the action performed with respect to the first node error counter for the device. The second node performs the action indicated in the message with respect to a second node error counter for the device indicated in the message, wherein the second node error counter corresponds to the first node error counter for the device.Type: GrantFiled: June 3, 2008Date of Patent: March 8, 2011Assignee: International Business Machines CorporationInventors: James Lamar Hood, Brian Anthony Rinaldi, Micah Robison, Todd Charles Sorenson
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Patent number: 7826380Abstract: An apparatus, system, and method are disclosed for data tracking and, in particular, for facilitating failure management within an electronic data communication system. The apparatus includes a tracking module and an error analysis module. The tracking module stores an adapter identifier in a tracking array. The adapter identifier corresponds to a source adapter from which data is received. The error analysis module determines a source of a data failure in response to recognition of the data failure. The data failure may occur on a host adapter, a device adapter, a communication fabric, a multi-processor, or another communication device. The apparatus, system, and method may be implemented in place of or in addition to hardware-assisted data integrity checking within a data storage system.Type: GrantFiled: March 30, 2005Date of Patent: November 2, 2010Assignee: International Business Machines CorporationInventors: Kevin John Ash, Susan Kay Candelaria, David Frank Mannenbach, Brian Anthony Rinaldi