Abstract: A method and apparatus for low cost set mapping in, for example, a computer graphics processor or communications device efficiently maps elements of one set into another set. When used in conjunction with a graphical display system the low cost set mapping logic enables a memory controller to efficiently communicate with a plurality of memory devices based upon a hierarchical computation scheme. The method and apparatus provide a pseudo-optimal mapping solution. By employing a pseudo-optimal mapping solution the low cost set mapping logic greatly reduces the computational resource required to perform the mapping operation.

Abstract: The present invention is generally directed to a circuit and method for evaluating the timing relationship of electrical signals in an integrated circuit. In accordance with one aspect of the invention, a circuit is provided having a signal select circuit that is includes two or more inputs and one output. The signal select circuit (preferably a multiplexer) is configured to select one of the two or more input signals for evaluation and direct it to the output. A plurality of signal buffers are electrically cascaded to the output of the signal select circuit. Finally, a scan chain having a plurality of scan elements is disposed to acquire a state of electrical signals along the plurality of signal buffers. In accordance with another aspect of the invention, a method is provided for evaluating the timing relationship of electrical signals in an integrated circuit.

Abstract: An improved system and method are provided for generating a design for a regular structure such as a memory array, multiplier array, or adder array embedded in a standard cell control block (SCCB). Once a net list has been generated for the SCCB by a logic synthesis tool, a special class of cells is created for the elements of the regular structure. The net list is modified via a special class mechanism by adding to the cells of the special class one or more special properties that are designed to optimize the placement of the cells of the regular structure. A modified placement and routing tool processes the modified net list by reading and interpreting the special properties so as to generate an improved design for the SCCB.

Abstract: Apparatus for electrically verifying a functional unit contained within an integrated circuit comprises a functional unit, a state machine, a number of integrated circuit input pins, and means for alternately providing the functional unit with control data derived from the state machine, and control data derived from the number of integrated circuit input pins. The means for providing control data from alternating sources comprises a multiplexor which receives a first set of inputs from the state machine, and a second set of inputs from a test control block. The test control block monitors various of the integrated circuit input pins for a designated instruction, receives control data via the input pins, and controls the operation of the multiplexor. The test control block comprises a number of test registers which can be configured to receive two or more states of control data.

Abstract: A minimal logic multiplexer system using tri-state drivers with one-hot enabling lead, provides high-speed access to processor elements by any one of a plurality of control units. The multiplexer system is implemented in a manner that minimizes the circuit implementation, minimizes gate delay within the circuit implementation, and allows processing instructions to pass from a control unit to the processor elements by way of multiplexed control lines therebetween. The multiplexer system contains control unit gate groups that are enabled and disabled in parallel by a select lead. Each control unit gate group can be implemented internal to the respective control unit or external in a common intermediary multiplexer circuit location.

Abstract: A CMOS latch circuit having a second feedback inverter and a switching circuit to switch the second feedback inverter out of the circuit when the latch is being loaded. A first circuit implementation uses a single PFET as the switching circuit, and a second circuit implementation incorporates an NFET transistor, in parallel with the PFET. In a third circuit implementation, the switching circuit switches power to and from the second feedback inverter rather than switching the output signal of the inverter to reduce the input capacitance of the latch.

Abstract: A dual transparent latch circuit is disclosed comprising two latches cross coupled together by two control lines to enable the latches collectively to input and output data at twice the frequency of the master clock frequency which controls the timing of each latch individually. The control lines are controlled by a clock generator such that one latch is enabled to receive and store data while the other latch is enabled to output data stored therein. At the same time, the latch receiving and storing the data is disabled from providing an output of the stored data and the latch providing the output is disabled from receiving and storing the data. The clock generator switches the states of the control lines such that they enable or disable the input of data to and output of data from the latches on each phase of the master clock signal. A dual transparent latch with triple edge timing is also disclosed.