Abstract: An apparatus includes a voltage regulator including a high-side field-effect transistor, a low-side field-effect transistor, an inductor, and a conductive net connecting the high-side field-effect transistor, the low-side field-effect transistor and the inductor. The apparatus further includes an attenuation circuit coupled to the conductive net, wherein the attenuation circuit includes an electronic switch that enables and disables an amount of attenuation provided by the attenuation circuit. Examples of the attenuation circuit include a snubber circuit and a boost resistor circuit.

Abstract: An apparatus includes a voltage regulator including a high-side field-effect transistor, a low-side field-effect transistor, an inductor, and a conductive net connecting the high-side field-effect transistor, the low-side field-effect transistor and the inductor. The apparatus further includes an attenuation circuit coupled to the conductive net, wherein the attenuation circuit includes an electronic switch that enables and disables an amount of attenuation provided by the attenuation circuit. Examples of the attenuation circuit include a snubber circuit and a boost resistor circuit.

Abstract: A computer program product and an apparatus are provided. The computer program product includes a computer readable medium and program instructions embodied therein, wherein the program instructions are executable by a processor to cause the processor to perform various operations. The operations include obtaining, for each phase in a voltage regulator having multiple phases, values of at least one operating parameter over a period of time. The operations further include determining, for each phase in the multi-phase voltage regulator, a wear score as a function of the obtained values of at least one operating parameter. Still further, the operations include selecting a default phase, from among the multiple phases, that has a wear score indicating that the phase has less cumulative wear than any of the other phases, and instructing the voltage regulator to turn on the selected phase as a default phase when only one phase is turned on.

Abstract: A method of determining power fault information using a voltage regulator-down (VRD) device having a fault-pin output. The method may include receiving a fault indication from one of a plurality of fault detection devices, correlating the received fault indication with a timing signal having a predetermined time duration, applying a voltage change on the fault-pin output of the VRD device for the predetermined time duration corresponding to the timing signal, and applying the voltage change on the fault-pin output to a plurality of fuses. Based on the predetermined time duration associated with the applied voltage change, the plurality of fuses may be blown according to a binary pattern indicative of a fault type associated with the fault indication.

Abstract: A computer program product and an apparatus are provided. The computer program product includes a computer readable medium and program instructions embodied therein, wherein the program instructions are executable by a processor to cause the processor to perform various operations. The operations include obtaining, for each phase in a voltage regulator having multiple phases, values of at least one operating parameter over a period of time. The operations further include determining, for each phase in the multi-phase voltage regulator, a wear score as a function of the obtained values of at least one operating parameter. Still further, the operations include selecting a default phase, from among the multiple phases, that has a wear score indicating that the phase has less cumulative wear than any of the other phases, and instructing the voltage regulator to turn on the selected phase as a default phase when only one phase is turned on.

Abstract: A method includes obtaining, for each phase in a voltage regulator having multiple phases, values of at least one operating parameter over a period of time. The method further includes determining, for each phase in the multi-phase voltage regulator, a wear score as a function of the obtained values of at least one operating parameter. Still further, the method includes selecting a default phase, from among the multiple phases, that has a wear score indicating that the phase has less cumulative wear than any of the other phases, and instructing the voltage regulator to turn on the selected phase as a default phase when only one phase is turned on.

Abstract: A method includes sensing, using a current sensing circuit of a voltage regulator, an apparent amount of current output from the voltage regulator and identifying a present value of at least one operating parameter for the voltage regulator. The method further includes determining at least one current sense correction factor as a function of the identified present value of the at least one operating parameter, and calculating a corrected amount of current output from the voltage regulator as a function of the apparent amount of the current output and the at least one current sense correction factor. Still further, the method includes reporting the corrected amount of current to an integrated circuit that receives current output from the voltage regulator. The method may be performed in an apparatus, such as a server, that includes the voltage regulator, a baseboard management controller, and the integrated circuit.

Abstract: A power supply and a server are disclosed. The power supply includes a voltage regulator (VR) and a control circuit (CC). The CC monitors the voltage on a power output of the VR, and enables the VR to supply power to the power output in response to the voltage on the power output being less than a threshold voltage level. The CC receives power from a power source even after the VR has been disabled. A server may include the power supply and the CC, as well as a CPU for executing an operating system (OS) and a baseboard management module for receive a virtual reseat request (VRR), request shutdown of the operating system in response to the VRR, enable the CC in response to the VRR, determine whether the OS has shut down, and disable the power supply in response to determining the OS has shut down.

Abstract: A method includes obtaining, for each phase in a voltage regulator having multiple phases, values of at least one operating parameter over a period of time. The method further includes determining, for each phase in the multi-phase voltage regulator, a wear score as a function of the obtained values of at least one operating parameter. Still further, the method includes selecting a default phase, from among the multiple phases, that has a wear score indicating that the phase has less cumulative wear than any of the other phases, and instructing the voltage regulator to turn on the selected phase as a default phase when only one phase is turned on.

Abstract: A method includes identifying a plurality of power supplies connected for supplying power to a computer system, wherein the plurality of power supplies includes at least one redundant power supply in a standby mode. For each of the plurality of power supplies identified, the method determines a length of a power supply cable connected between the power supply and a power distribution unit for supplying power to the power supply. The method further includes placing one or more of the plurality of power supplies in an active mode in ascending order of the length of the cable connected to the power supply, and supplying power to the computer system using the one or more of the plurality of power supplies in the active mode.

Abstract: Controlling power consumption of a voltage regulator in a computer system that includes computer memory and the voltage regulator is configured to provide regulated source voltage to the computer memory includes: receiving, by a voltage regulator controller, memory margin statistics of the computer memory, the memory margin statistics including data describing operational tolerance of the computer memory to source voltage signal variations; and adjusting, by the voltage regulator controller, one or more operating characteristics of the voltage regulator in dependence upon the memory margin statistics.

Abstract: A method of controlling the inrush current to a hot plug device. The method includes directing current from an input power rail of the hot plug device to an output power rail of the hot plug device through a high impedance auxiliary current path, wherein an electronic subsystem of the hot plug device is coupled to the output power rail. The method further includes allowing current from the input power rail to pass through a plurality of main turn on FETs to the output power rail in response to the output power rail having a voltage that exceeds a voltage threshold as a result of directing current through the high impedance auxiliary current path.

Abstract: A method includes performing operations on a compute node including a plurality of processors each having a local PCI processing element and a local processor interconnect, wherein the local processor interconnect of each processor is connected to the local processor interconnect of at least one other processor. The method further includes identifying a PCI device that is directly attached to the local PCI processing element of a first one of the processors and positioned in an upstream airflow direction from the first processor. The operating system monitors the PCI device and, in response to determining that the PCI device is performing a power-intensive operation, directs operations away from the first processor to a second one of the processors, wherein the local processor interconnect of the second processor is directly connected to the processor interconnect of the first processor.

Abstract: A hot plug device includes an electronic subsystem and a plurality of main turn on FETs, wherein each main turn on FET includes a gate, a power input for coupling to a power source, and an output for controllably providing power to the electronic subsystem. An auxiliary current path is in parallel with the main turn on FETs and includes a fuse, an impedance element and an auxiliary turn on FET. A turn on controller controls the main turn on FETs and the auxiliary turn on FET. Current is initially through the high impedance auxiliary current path to apply voltage to an output power rail. Subsequently, current is allowed to pass through a plurality of main turn on FETs to the output power rail in response to the output power rail having a voltage exceeding a voltage threshold as a result of using the high impedance auxiliary current path.

Abstract: A method includes a plurality of voltage regulators distributing power to a plurality of components within a compute node, wherein each of the voltage regulators has a controller, volatile memory and non-volatile memory. The controller of each voltage regulator temporarily caches operating data for the voltage regulator in the volatile memory of the voltage regulator, wherein the controller temporarily caches the operating data collected from the voltage regulator over a sliding time period. When a first voltage regulator from among the plurality of voltage regulators experiences a fault event, the controller of each voltage regulator detects the fault event and automatically copies the cached operating data for the voltage regulator from the volatile memory of the voltage regulator to the non-volatile memory of the voltage regulator in response to detecting the fault event.

Abstract: A computer program product includes a computer readable storage medium having program instructions embodied therewith, wherein the program instructions are executable by a processor to cause the processor to perform a method. The method comprises obtaining an activity level for each of a plurality of functions of an integrated circuit, wherein each function has a different physical location on the integrated circuit. The method further includes dynamically adjusting an amount of current supplied to the integrated circuit by each of a plurality of power stages of a DC voltage regulator to meet the current requirements of the plurality of functions and to control power losses between the power stages and the functions, wherein each power stage has a different physical location along a perimeter of the integrated circuit.

Abstract: A DC-DC converter includes a directly coupled inductor with coil elements and power-switching phases. Each phase includes a high-side and low-side switch, where the high-side switch couples a voltage source to a coil element and the low-side switch couples the coil element to a ground voltage. Each switch is configured to be alternately activated and no two switches are activated at the same time. A current sensor for the DC-DC converter includes a single current amplifier having inputs and an output. The output provides a current sensing signal. The current sensor also includes a single RC network coupled to one of the power-switching phases and a first input of the current amplifier. The current sensor also includes a resistive ladder. The ladder includes, for each of the other power-switching phases, a resistor coupled in parallel to the RC network resistor and to a second input of the current amplifier.

Abstract: A computer system includes power-consuming components, a power supply providing power to the power-consuming components, a single power bus extending from the power supply to each of the system components, and a service processor in communication with the components and the power supply. The service processor sends a turn on signal to the power supply in response to detecting activity of the power-consuming components and sends a sleep mode signal to the power supply in response to detecting inactivity of the power-consuming components. The power supply supplies power to the single power bus at a first voltage in response to receiving the turn on signal and supplies power to the single power bus at a second voltage in response to receiving the sleep mode signal, wherein the first voltage is greater than the second voltage.

Abstract: A method includes a plurality of voltage regulators distributing power to a plurality of components within a compute node, wherein each of the voltage regulators has a controller, volatile memory and non-volatile memory. The controller of each voltage regulator temporarily caches operating data for the voltage regulator in the volatile memory of the voltage regulator, wherein the controller temporarily caches the operating data collected from the voltage regulator over a sliding time period. When a first voltage regulator from among the plurality of voltage regulators experiences a fault event, the controller of each voltage regulator detects the fault event and automatically copies the cached operating data for the voltage regulator from the volatile memory of the voltage regulator to the non-volatile memory of the voltage regulator in response to detecting the fault event.

Abstract: A method includes identifying a plurality of power supplies connected for supplying power to a computer system, wherein the plurality of power supplies includes at least one redundant power supply in a standby mode. For each of the plurality of power supplies identified, the method determines a length of a power supply cable connected between the power supply and a power distribution unit for supplying power to the power supply. The method further includes placing one or more of the plurality of power supplies in an active mode in ascending order of the length of the cable connected to the power supply, and supplying power to the computer system using the one or more of the plurality of power supplies in the active mode.