Patents by Inventor Brian Chess

Brian Chess has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030182357
    Abstract: The present invention relates to Internet based and web applications and the need to reduce page latency and bandwidth usage. The invention can achieve these goals by making use of the cache built in to standard web browsers. In one embodiment, the invention provides that a web application user will use their browser to request a page from the application web server, which responds with a small page that includes a script. The script appends a previously established cookie value to the URL originally requested and the browser then re-requests the URL with the appended cookie value. (The server computes the cookie value based on the last modified time of the data used to generate the page.) If the most recent version of the page is in the browser cache, the browser gets a cache hit, which means the page is retrieved from browser cache rather than from the server, rapidly displaying the page to the user.
    Type: Application
    Filed: March 1, 2002
    Publication date: September 25, 2003
    Inventors: Brian Chess, Evan Goldberg, William Ellery Bailey
  • Patent number: 6560736
    Abstract: A method for diagnosing bridging faults with inexpensively-obtained stuck-at signatures, in which only those faults determined to be realistic through inductive fault analysis are considered as candidates, match restrictions and match requirements are imposed during matching in order to minimize diagnosis size, and match ranking is applied and the matching criteria relaxed to further increase the effective precision and to increase the number of correct diagnoses. In addition, the method reduces the number of bridging fault candidates by constructing a dictionary of composite signatures of node pairs based on a ranking threshold.
    Type: Grant
    Filed: January 10, 2001
    Date of Patent: May 6, 2003
    Assignee: The Regents of the University of California
    Inventors: F. Joel Ferguson, Tracy Larabee, Brian Chess, David B. Lavo
  • Publication number: 20010003427
    Abstract: A method for diagnosing bridging faults with inexpensively-obtained stuck-at signatures, in which only those faults determined to be realistic through inductive fault analysis are considered as candidates, match restrictions and match requirements are imposed during matching in order to minimize diagnosis size, and match ranking is applied and the matching criteria relaxed to further increase the effective precision and to increase the number of correct diagnoses. In addition, the method reduces the number of bridging fault candidates by constructing a dictionary of composite signatures of node pairs based on a ranking threshold.
    Type: Application
    Filed: January 10, 2001
    Publication date: June 14, 2001
    Inventors: F. Joel Ferguson, Tracy Larrabee, Brian Chess, David B. Lavo
  • Patent number: 6202181
    Abstract: A method for diagnosing bridging faults with inexpensively-obtained stuck-at signatures, in which only those faults determined to be realistic through inductive fault analysis are considered as candidates, match restrictions and match requirements are imposed during matching in order to minimize diagnosis size, and match ranking is applied and the matching criteria relaxed to further increase the effective precision and to increase the number of correct diagnoses. In addition, the method reduces the number of bridging fault candidates by constructing a dictionary of composite signatures of node pairs based on a ranking threshold.
    Type: Grant
    Filed: November 3, 1997
    Date of Patent: March 13, 2001
    Assignee: The Regents of the University of California
    Inventors: F. Joel Ferguson, Tracy Larabee, Brian Chess, David B. Lavo
  • Patent number: 5914615
    Abstract: A method of detecting defects within an integrated circuit. Iddq testing for defects within integrated circuits includes measuring the quiescent (Iddq) current conducted by power supply nodes of the integrated circuit which are connected to a power supply while controlling signal levels of a plurality of inputs to the integrated circuit. The method of this invention includes calculating an upper threshold Iddq value and a lower threshold Iddq value. The input nodes are driven to a predetermined combination of input voltages and a corresponding Iddq value is measured. It is determined whether the measured Iddq value is between the upper threshold Iddq value and the lower threshold Iddq value. Another embodiment of this invention includes the upper and lower threshold values being dependent on a measured mean value of Iddq for the integrated circuit.
    Type: Grant
    Filed: April 29, 1997
    Date of Patent: June 22, 1999
    Assignee: Hewlett-Packard Company
    Inventor: Brian Chess