Patents by Inventor Brian Cleereman

Brian Cleereman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods of forming memory; and methods of forming vertical structures
    Patent number: 8609489
    Abstract: Some embodiments include methods of forming memory. A series of photoresist features may be formed over a gate stack, and a placeholder may be formed at an end of said series. The placeholder may be spaced from the end of said series by a gap. A layer may be formed over and between the photoresist features, over the placeholder, and within said gap. The layer may be anisotropically etched into a plurality of first vertical structures along edges of the photoresist features, and into a second vertical structure along an edge of the placeholder. A mask may be formed over the second vertical structure. Subsequently, the first vertical structures may be used to pattern string gates while the mask is used to pattern a select gate. Some embodiments include methods of forming conductive runners, and some embodiments may include semiconductor constructions.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: December 17, 2013
    Assignee: Micron Technology, Inc.
    Inventors: David A. Kewley, Brian Cleereman, Stephen W. Russell, Rex Stone, Anthony C. Krauth
  • Methods of Forming Memory; and Methods of Forming Vertical Structures
    Publication number: 20110237081
    Abstract: Some embodiments include methods of forming memory. A series of photoresist features may be formed over a gate stack, and a placeholder may be formed at an end of said series. The placeholder may be spaced from the end of said series by a gap. A layer may be formed over and between the photoresist features, over the placeholder, and within said gap. The layer may be anisotropically etched into a plurality of first vertical structures along edges of the photoresist features, and into a second vertical structure along an edge of the placeholder. A mask may be formed over the second vertical structure. Subsequently, the first vertical structures may be used to pattern string gates while the mask is used to pattern a select gate. Some embodiments include methods of forming conductive runners, and some embodiments may include semiconductor constructions.
    Type: Application
    Filed: June 6, 2011
    Publication date: September 29, 2011
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: David A. Kewley, Brian Cleereman, Stephen W. Russell, Rex Stone, Anthony C. Krauth
  • Methods of forming memory cells; and methods of forming vertical structures
    Patent number: 7972926
    Abstract: Some embodiments include methods of forming memory. A series of photoresist features may be formed over a gate stack, and a placeholder may be formed at an end of said series. The placeholder may be spaced from the end of said series by a gap. A layer may be formed over and between the photoresist features, over the placeholder, and within said gap. The layer may be anisotropically etched into a plurality of first vertical structures along edges of the photoresist features, and into a second vertical structure along an edge of the placeholder. A mask may be formed over the second vertical structure. Subsequently, the first vertical structures may be used to pattern string gates while the mask is used to pattern a select gate. Some embodiments include methods of forming conductive runners, and some embodiments may include semiconductor constructions.
    Type: Grant
    Filed: July 2, 2009
    Date of Patent: July 5, 2011
    Assignee: Micron Technology, Inc.
    Inventors: David A. Kewley, Brian Cleereman, Stephen W. Russell, Rex Stone, Anthony C. Krauth
  • Methods Of Forming Memory Cells; And Methods Of Forming Vertical Structures
    Publication number: 20110003469
    Abstract: Some embodiments include methods of forming memory. A series of photoresist features may be formed over a gate stack, and a placeholder may be formed at an end of said series. The placeholder may be spaced from the end of said series by a gap. A layer may be formed over and between the photoresist features, over the placeholder, and within said gap. The layer may be anisotropically etched into a plurality of first vertical structures along edges of the photoresist features, and into a second vertical structure along an edge of the placeholder. A mask may be formed over the second vertical structure. Subsequently, the first vertical structures may be used to pattern string gates while the mask is used to pattern a select gate. Some embodiments include methods of forming conductive runners, and some embodiments may include semiconductor constructions.
    Type: Application
    Filed: July 2, 2009
    Publication date: January 6, 2011
    Inventors: David A. Kewley, Brian Cleereman, Stephen W. Russell, Rex Stone, Anthony C. Krauth