Abstract: A multi-chip system and method are disclosed for incorporating a primitive assembler in each of one or more geometry chips and one or more rasterization chips. This system may allow per-primitive operations to be performed in the geometry chips, and also allow use of a vertex data interface for sending vertex data to the rasterization chips. The primitive assemblers in the geometry chips may assemble vertices into primitives for clipping tests. The geometry chips may also test an assembled primitive against the projected boundaries of a set of screen space regions, where each region is assigned to one of the rasterization chips. Those primitives residing in more than one region may be sub-divided into two or more new primitives so that each new primitive resides in only one screen space region. The geometry chip may then send the vertex data for each primitive to the corresponding rasterization chip.

Abstract: A method and system for synchronizing data streams and transferring control of resources between two processes in a graphics processor is described. The method allows for completion of pending operations of a first process in a manner that ensures the first process may be restarted without loss of data or process sequence. The processing pipeline is allowed to complete normal execution of all process operations required to reach a first process step that may be interrupted. The second process is initiated when the interruption of the first process is verified. Upon completion of the second process, the first process is reactivated at the next process step in sequence.

Abstract: A cache memory with improved cache-miss performance is implemented by providing cache-miss data from system memory directly to its requester. One embodiment of the invention operates as a texture cache in a graphics system. The graphics system comprises a system memory that stores texture data, coupled to a texture cache memory, which is coupled to at least one requester. The texture cache memory is divided into a cache tags unit and a data cache unit. The data cache unit is configured to receive at least two cache address inputs, and has at least two data output ports each coupled to a respective first input of a respective multiplexer. A respective second input of each multiplexer is configured to receive cache-miss data from the system memory. The select input of each multiplexer is configured to receive a respective hit/miss indicator signal associated with the respective cache address input. In case of a cache-miss, cache-miss data from system memory bypasses the data cache unit and is output directly.

Abstract: Cache access is optimized through identifying redundant accesses (read-requests made to identical system memory addresses), and issuing a single cache data request for each group of redundant accesses. One embodiment of the invention is a graphics system comprising a system memory that stores texture data, coupled to a texture cache that is coupled to one or more texture pipes. Each pipe processes information for a respective spatial bin. A cache preprocessor receives read-requests for texels from the texture pipes and generates a control code corresponding to each read-request, indicating whether the read-request is a redundant access, and linking redundant accesses to a single cache data request. The cache preprocessor provides the control codes and the read-requests to a cache arbiter, which issues the codes and the cache data requests to the texture cache.

Abstract: A graphics system and method for storing and accessing texture maps comprising texels. The graphics system may include a graphics processor and a texture memory comprising a plurality of memory devices for storing the texture maps. The texels (or portions of the texels) may be stored in the memory devices in an interleaved fashion. The texel data is interleaved in the memory devices to guarantee that, no matter which N×M array of texels is accessed, each texel in the array is present in a different memory device or chip and hence are concurrently available. Thus the N×M array of texels may be output concurrently or simultaneously, regardless of which array is accessed, i.e., regardless of which pixel is addressed. Embodiments are also described where the memory devices output arrays of texels for at least two respective neighboring pixels, or a 3D array of texels, in parallel in response to a single read transaction.

Abstract: An optimizing unit for use with an interleaved memory and suitable for use in a computer graphics system is described. The unit utilizes knowledge of the repetitive and predictable nature of texture buffer accesses to potentially reduce the number of memory fetches. The unit maintains a queue of pending requests for tiles of data from the memory, and predicts the retrieval of redundant data within short sequences of requests. The redundant data is retrieved from the memory once, and repeated as necessary from local temporary storage registers.

Abstract: A method for optimizing a cache memory used for multitexturing in a graphics system is implemented. The graphics system comprises a texture memory, which stores texture data comprised in texture maps, coupled to a texture cache memory. Active texture maps for an individual primitive, for example a triangle, are identified, and the texture cache memory is divided into partitions. In one embodiment, the number of texture cache memory partitions equals the number of active texture maps. Each texture cache memory partition corresponds to a respective single active texture map, and is operated as a direct mapped cache for its corresponding respective single active texture map. In one embodiment, each texture cache memory partition is further operated as an associative cache for the texture data comprised in the partition's corresponding respective single active texture map. The cache memory is dynamically re-configured for each primitive.

Abstract: A predictive memory performance optimizing unit for use with an interleaved memory, for example a DDR SDRAM memory, and suitable for use in a computer graphics system, among others, is described. The unit maintains a queue of pending requests for data from the memory, and prioritizes precharging and activating interleaves with pending requests. Interleaves which are in a ready state may be accessed independently of the precharging and activation of non-ready interleaves. The unit utilizes idle cycles occurring between consecutive requests to activate interleaves with pending requests.

Abstract: A rendering unit positions a supertile so that it intersects a primitive. The rendering unit repeatedly walks over bins of the supertile, applying a layer of texture to the bins of the supertile in each iteration of said repeated walking. The rendering unit advances to the next texture layer after having applied the current texture layer to each candidate bin of the supertile. The results of each texture layer application to the bins may be stored in a texture accumulation buffer. The size of the supertile corresponds to the size of the texture accumulation buffer. After applying a last layer of texture to the bins of the supertile, the supertile may be advanced to a new position. The rendering unit traverses the primitive with the supertile so that the union of areas visited by the supertile covers the primitive.

Abstract: An integrated circuit including logic for testing internal operation of the integrated circuit. The integrated circuit may comprise a plurality of internal functional blocks coupled by a plurality of internal buses. The integrated circuit may also comprise a set of test control input pins and a set of test output pins comprised on the integrated circuit. The integrated circuit may comprise selection logic. The selection logic comprises inputs coupled to various ones of the internal buses, an output coupled to the set of test output pins, and a select input coupled to receive select signals from the set of test control input pins. The selection logic is operable to select internal bus signals from an internal bus based on the select signals from the test control input pins, and the selection logic is configured to output the selected internal bus signals to the set of test output pins.

Abstract: A programmable filter comprising a tree of computational units, where each computational unit is configured to receive multiple inputs and generate multiple outputs, where the tree receives a set of input operands and generates output operands, where, in a sum of products mode, the output operands of the tree comprise a sum of products of the input operands by corresponding N-bit coefficients, where N is a positive integer, where, in a linear interpolation mode, each of the output operands of the tree comprise linear interpolations of at least two of the input operands, wherein coefficients of the linear interpolations have (N/2) bits of precision.

Abstract: The propagation of a feedback signal, such as a DQS signal generated in response to a read request in a Double Data Rate (DDR) memory system, into a digital host system, such as an ASIC, is controlled by using a programmable delay circuit and detection sequence to compensate for variable I/O delay. The memory system includes a controller and an interface, both on the ASIC, and memory units coupled to the controller through the interface. The interface uses the read request signal, sent by the controller to initiate read operations, to generate a select signal. A programmable delay element inside the interface unit is programmed using a delay value generated by a delay manager unit inside the controller. The programmable delay element delays the select signal, and an enable signal is generated from the delayed select signal, using DQS. The propagation of DQS is controlled by the enable signal.

Abstract: Data, such as data received by a memory I/O from a memory unit in a DDR SDRAM system, is captured using a trigger signal, which may be a non free-running clock signal such as a DQS signal in a DDR SDRAM system, and is transferred to a host system, which may be part of an ASIC, using the host system's clock. The memory I/O includes a data capture register that latches the data received from the memory unit using DQS. The memory I/O also includes a FIFO buffer that latches the data output by the data capture register using a delayed version of DQS. A single edge of the delayed DQS is available to the FIFO for latching each set of data that corresponds to a single pulse of DQS. The FIFO transfers the data to the host system using the host system's clock, which represents a different clock domain than DQS.

Abstract: The propagation of a feedback signal, such as a DQS signal generated in response to a read request in a Double Data Rate (DDR) memory system, into a digital host system, such as an ASIC, is controlled by using delay tracking to compensate for variable I/O delay. The memory system includes a controller and an interface, both on the ASIC, and memory units coupled to the controller through the interface, all configured on a printed circuit board (PCB). The interface uses the read request signal, sent by the controller to initiate read operations, to generate a read-enable signal, which is transmitted to a trace on the PCB one-half cycle of the system clock before DQS is expected to reach the interface. The trace tracks the total delay encountered by the system clock and DQS between the interface unit and memory units, and is routed back to the interface unit, where read-enable is used to generate an enable signal that allows DQS to propagate into the ASIC only when DQS is a valid digital signal.

Abstract: A predictive optimizing unit for use with an interleaved memory and suitable for use in a computer graphics system is described. The unit maintains a queue of pending requests for data from the memory, and prioritizes precharging and activating interleaves with pending requests. Interleaves which are in a ready state may be accessed independently of the precharging and activation of non-ready interleaves.

Abstract: An integrated circuit may include several components, one or more interfaces, an interconnect (e.g., a bus), and a controller. The components may each be configured to assert a read request to read data stored externally to the integrated circuit. The interfaces may be configured to output the read request asserted by one of the components and to receive data in response to outputting the request. The interconnect may be coupled to perform one or more data transactions to transmit the data from one of the interfaces to one or more of the components. In response to the read request asserted by one of the components, the controller may inhibit performance of a read transaction initiated by the read request dependent upon a comparison of a total number of outstanding data transactions to a maximum allowable number of outstanding data transactions.

Abstract: A graphics system may include a frame buffer, a processing device coupled to output data, a multipurpose memory device that includes a plurality of storage locations and is coupled to store data output from the processing device, and a multipurpose memory controller coupled to the multipurpose memory device. The multipurpose memory controller may be configured to allocate a first plurality of the storage locations to a first image buffer configured to store image data, a second plurality of the storage locations to a first texture buffer configured to store texture data, and a third plurality of the storage locations to a first accumulation buffer configured to store accumulation buffer data. The multipurpose memory device may be configured to include a first image buffer, a first texture buffer, and a first accumulation buffer at the same time.

Abstract: A graphics system and method for storing and accessing texture maps comprising texels. The graphics system may include a graphics processor and a texture memory comprising a plurality of memory devices for storing the texture maps. The texels (or portions of the texels) may be stored in the memory devices in an interleaved fashion. The texel data is interleaved in the memory devices to guarantee that, no matter which N×M array of texels is accessed, each texel in the array is present in a different memory device or chip and hence are concurrently available. Thus the N×M array of texels may be output concurrently or simultaneously, regardless of which array is accessed, i.e., regardless of which pixel is addressed. Embodiments are also described where the memory devices output arrays of texels for at least two respective neighboring pixels, or a 3D array of texels, in parallel in response to a single read transaction.

Abstract: A system and a method for improving magnified texture-mapped pixel performance in a single-pixel pipeline. Two textured pixel addresses corresponding to two pixels may be generated. The two textured pixel addresses may then be passed to the next unit in the pipeline, where the two textured pixel addresses can be examined if the corresponding two pixels correspond to a common set of texels in texture space. The two textured pixel addresses may be merged together if the two pixels correspond to the common set of texels. Merging may operate to create a combined texel structure. Texel data may be generated in response to receiving the combined texel structure. The texel data may be filtered using one or more texture filters in order to generate texture values.

Abstract: An integrated circuit may include several components, one or more interfaces, an interconnect (e.g., a bus), and a controller. The components may each be configured to assert a read request to read data stored externally to the integrated circuit. The interfaces may be configured to output the read request asserted by one of the components and to receive data in response to outputting the request. The interconnect may be coupled to perform one or more data transactions to transmit the data from one of the interfaces to one or more of the components. In response to the read request asserted by one of the components, the controller may inhibit performance of a read transaction initiated by the read request dependent upon a comparison of a total number of outstanding data transactions to a maximum allowable number of outstanding data transactions.