Patents by Inventor Brian D. Rauchfuss
Brian D. Rauchfuss has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9996386Abstract: Methods and apparatus relating to mid-thread pre-emption with software assisted context switch are described. In an embodiment, one or more threads executing on a Graphics Processing Unit (GPU) are stopped at an instruction level granularity in response to a request to pre-empt the one or more threads. The context data of the one or more threads is copied to memory in response to completion of the one or more threads at the instruction level granularity and/or one or more instructions. Other embodiments are also disclosed and claimed.Type: GrantFiled: July 23, 2014Date of Patent: June 12, 2018Assignee: Intel CorporationInventors: Brian D. Rauchfuss, Naveen R. Matam, Michael K. Dwyer, Aditya Navale
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Publication number: 20160026494Abstract: Methods and apparatus relating to mid-thread pre-emption with software assisted context switch are described. In an embodiment, one or more threads executing on a Graphics Processing Unit (GPU) are stopped at an instruction level granularity in response to a request to pre-empt the one or more threads. The context data of the one or more threads is copied to memory in response to completion of the one or more threads at the instruction level granularity and/or one or more instructions. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: July 23, 2014Publication date: January 28, 2016Applicant: Intel CorporationInventors: BRIAN D. RAUCHFUSS, NAVEEN R. MATAM, MICHAEL K. DWYER, ADITYA NAVALE
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Publication number: 20130307860Abstract: In accordance with some embodiments, a fixed function media accelerator may be preempted in the middle of processing one frame of data and still be able to resume operation later without the need to save an internal state. This ability to be preempted, without saving an internal state, may be important for supporting page fault and increasing the responsiveness of fixed function engines. Enabling preemption without the need to save the entire state reduces the complexity of the implementation in some embodiments.Type: ApplicationFiled: March 30, 2012Publication date: November 21, 2013Inventors: Mostafa Hagog, Eran Shifer, Scott W. Cheng, Brian D. Rauchfuss, Eli Turiel
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Publication number: 20130266080Abstract: Methods, systems and computer program products to increase the efficiency of a trancoding system by providing additional data from a video processor to an encoder, and by providing control signals from the encoder back to the video processor. The video processor may provide variances to the encoder, where these values would not otherwise be available to the encoder or would be computationally intensive for the encoder to generate on its own. The encoder may then use these variances to generate encoded, compressed video data more efficiently. The encoder may also generate control signals for use by the video processor, enabling the video processor to adapt to reconfigurations of the encoder, thereby improving the efficiency of the transcoding operation.Type: ApplicationFiled: October 1, 2011Publication date: October 10, 2013Inventors: Ning Lu, Brian D. Rauchfuss, Sang-Hee Lee, Yi-Jen Chiu
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Patent number: 8544019Abstract: In some embodiments, a method includes receiving a request to generate a thread and supplying a request to a queue in response at least to the received request. The method may further include fetching a plurality of instructions in response at least in part to the request supplied to the queue and executing at least one of the plurality of instructions. In some embodiments, an apparatus includes a storage medium having stored therein instructions that when executed by a machine result in the method. In some embodiments, an apparatus includes circuitry to receive a request to generate a thread and to queue a request to generate a thread in response at least to the received request. In some embodiments, a system includes circuitry to receive a request to generate a thread and to queue a request to generate a thread in response at least to the received request, and a memory unit to store at least one instruction for the thread.Type: GrantFiled: May 26, 2011Date of Patent: September 24, 2013Assignee: Intel CorporationInventors: Hong Jiang, Thomas A. Piazza, Brian D. Rauchfuss, Sreedevi Chalasani, Steven J. Spangler
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Publication number: 20110314479Abstract: In some embodiments, a method includes receiving a request to generate a thread and supplying a request to a queue in response at least to the received request. The method may further include fetching a plurality of instructions in response at least in part to the request supplied to the queue and executing at least one of the plurality of instructions. In some embodiments, an apparatus includes a storage medium having stored therein instructions that when executed by a machine result in the method. In some embodiments, an apparatus includes circuitry to receive a request to generate a thread and to queue a request to generate a thread in response at least to the received request. In some embodiments, a system includes circuitry to receive a request to generate a thread and to queue a request to generate a thread in response at least to the received request, and a memory unit to store at least one instruction for the thread.Type: ApplicationFiled: May 26, 2011Publication date: December 22, 2011Inventors: Hong Jiang, Thomas A. Piazza, Brian D. Rauchfuss, Sreedevi Chalasani, Steven J. Spangler
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Patent number: 7975272Abstract: In some embodiments, a method includes receiving a request to generate a thread and supplying a request to a queue in response at least to the received request. The method may further include fetching a plurality of instructions in response at least in part to the request supplied to the queue and executing at least one of the plurality of instructions. In some embodiments, an apparatus includes a storage medium having stored therein instructions that when executed by a machine result in the method. In some embodiments, an apparatus includes circuitry to receive a request to generate a thread and to queue a request to generate a thread in response at least to the received request. In some embodiments, a system includes circuitry to receive a request to generate a thread and to queue a request to generate a thread in response at least to the received request, and a memory unit to store at least one instruction for the thread.Type: GrantFiled: December 30, 2006Date of Patent: July 5, 2011Assignee: Intel CorporationInventors: Hong Jiang, Thomas A. Piazza, Brian D. Rauchfuss, Sreedevi Chalasani, Steven J. Spangler
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Patent number: 7904701Abstract: Provided are a method and system for activating a design test mode in a graphics card having multiple execution units. A design test mode is activated in a graphics module comprising multiple execution units coupled to a cache on a bus. The bus is configured to return test instructions from the cache to the execution units in response to a request from one execution unit for the test instructions from the cache in the design test mode. The execution units execute the test instructions during the design test mode. Interrupts are prevented during the design test mode.Type: GrantFiled: June 7, 2007Date of Patent: March 8, 2011Assignee: Intel CorporationInventors: Anthony Babella, Allan Wong, Lance Cheney, Brian D. Rauchfuss
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Publication number: 20080307261Abstract: Provided are a method and system for activating a design test mode in a graphics card having multiple execution units. A design test mode is activated in a graphics module comprising multiple execution units coupled to a cache on a bus. The bus is configured to return test instructions from the cache to the execution units in response to a request from one execution unit for the test instructions from the cache in the design test mode. The execution units execute the test instructions during the design test mode. Interrupts are prevented during the design test mode.Type: ApplicationFiled: June 7, 2007Publication date: December 11, 2008Inventors: Anthony BABELLA, Allan WONG, Lance CHENEY, Brian D. RAUCHFUSS
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Publication number: 20080163215Abstract: In some embodiments, a method includes receiving a request to generate a thread and supplying a request to a queue in response at least to the received request. The method may further include fetching a plurality of instructions in response at least in part to the request supplied to the queue and executing at least one of the plurality of instructions. In some embodiments, an apparatus includes a storage medium having stored therein instructions that when executed by a machine result in the method. In some embodiments, an apparatus includes circuitry to receive a request to generate a thread and to queue a request to generate a thread in response at least to the received request. In some embodiments, a system includes circuitry to receive a request to generate a thread and to queue a request to generate a thread in response at least to the received request, and a memory unit to store at least one instruction for the thread.Type: ApplicationFiled: December 30, 2006Publication date: July 3, 2008Inventors: Hong Jiang, Thomas A. Piazza, Brian D. Rauchfuss, Sreedevi Chalasani, Steven J. Spangler
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Patent number: 6816167Abstract: An anisotropic filtering technique includes defining pixel elements in two dimensions and defining at least one object having three dimensional surfaces in a three-dimensional model space and storing texel elements in two dimensions defining a texture map bearing a relationship to the three dimensional surfaces of the at least one object. Each pixel element to be texture mapped is divided into a group of sub-pixel elements and the sub-pixel elements are separately texture mapped. The resultant textures of the sub-pixel elements are averaged to obtain a texture for their respective pixel element.Type: GrantFiled: January 10, 2000Date of Patent: November 9, 2004Assignee: Intel CorporationInventors: Brian D. Rauchfuss, Val Cook, Tom Piazza
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Patent number: 5301269Abstract: A circuit for performing window-relative dithering of intensity data comprises a programmable dither cell; circuitry for comparing dither values stored in the dither cell with selected parts of the intensity values and outputting an increment signal in accordance with the results of the comparison; a wrap prevention circuit for preventing the intensity from being incremented if incrementing would cause the intensity to wrap to a low value; and an adder for incrementing the intensity in response to the increment signal, provided it is not inhibited by the wrap prevention circuit. The dither circuit may be advantageously employed in a computer graphics system to dither pixel intensity values.Type: GrantFiled: March 15, 1991Date of Patent: April 5, 1994Assignee: Hewlett-Packard CompanyInventors: Byron A. Alcorn, Robert W. Cherry, Mark D. Coleman, Brian D. Rauchfuss
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Patent number: 5297251Abstract: A method of moving blocks of pixel data, including window-identifying data, from a source area to a destination area within a frame buffer in a computer graphics system comprises the steps of: reading a block of pixel data from the source area into a pixel cache memory; combining source tiles with destination tiles in the cache; comparing pixel window identifiers read from the frame buffer with a pixel window identifier previously stored in the memory to determine whether the pixel window identifiers read from the frame buffer match the previously stored pixel window identifier; discarding each pixel whose corresponding window identifier does not match the previously stored window identifier; and updating the frame buffer with the pixel data not discarded.Type: GrantFiled: May 6, 1991Date of Patent: March 22, 1994Assignee: Hewlett-Packard CompanyInventors: Byron A. Alcorn, Robert W. Cherry, Mark D. Coleman, Brian D. Rauchfuss
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Patent number: 5295245Abstract: A three-dimensional pixel cache for use in a computer graphics system comprises source, pattern, and destination tile caches and a barrel shift register, or rotator, that serves as an interface between the tile caches and a frame buffer. The rotator has the capability of performing three types of rotation of data read/written from/to the tile caches horizontal rotation, vertical rotation, and rotation of nibbles within each pixel.Type: GrantFiled: March 15, 1991Date of Patent: March 15, 1994Assignee: Hewlett-Packard CompanyInventors: Byron A. Alcorn, Robert W. Cherry, Mark D. Coleman, Brian D. Rauchfuss
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Patent number: 5193148Abstract: A method of moving blocks of pixel data, including window-identifying data, from a source area to a destination area within a frame buffer in a computer graphics system comprises the steps of: reading a block of pixel data from the source area into a pixel cache memory; combining source tiles with destination tiles in the cache; comparing pixel window identifiers read from the frame buffer with a pixel window identifier previously stored in the memory to determine whether the pixel window identifiers read from the frame buffer match the previously stored pixel window identifier; discarding each pixel whose corresponding window identifier does not match the previously stored window identifier; and updating the frame buffer with the pixel data not discarded.Type: GrantFiled: December 4, 1991Date of Patent: March 9, 1993Assignee: Hewlett-Packard CompanyInventors: Byron A. Alcorn, Robert W. Cherry, Mark D. Coleman, Brian D. Rauchfuss
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Patent number: 5185856Abstract: Pixel arithmetic and logical units for rendering pixels in graphics systems. Circuits for performing arithmetic operations on raster scan data are provided. The circuits comprise opcode registers for selecting an arithmetic function which transforms pixel value data corresponding to graphics primitives, multiplication circuits interfaced with the opcode registers for multiplying graphics operators with graphics data to obtain transform pixel value data, combining circuits interfaced with the multiplication circuits for adding transform pixel value data to existing pixel value data and processing circuitry interfaced with the combining circuitry for storing overflow data from the combining circuitry when adding transform pixel data overflows the combining circuitry.Type: GrantFiled: March 16, 1990Date of Patent: February 9, 1993Assignee: Hewlett-Packard CompanyInventors: Byron A. Alcorn, Robert W. Cherry, Mark D. Coleman, Brian D. Rauchfuss
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Patent number: 5012163Abstract: Methods and apparatus for providing pixel brightness correction in monitors. The methods and apparatus disclosed herein provide significant cost reductions in gamma correction circuitry by first degamma correcting pixel value data stored on a frame buffer, and then gamma correcting the degamma corrected pixel value data before the data is stored back on the frame buffer. Circuits for providing pixel brightness correction in a monitor comprise logic circuits for generating upper bits of a data word representing pixel intensity, shifter circuits interfaced with the logic circuits for generating lower bits of the data word representing pixel intensity, and combining circuits interfaced with the logic circuits and the shifter circuits for generating intermediate bits of the data word representing pixel intensity.Type: GrantFiled: March 16, 1990Date of Patent: April 30, 1991Assignee: Hewlett-Packard Co.Inventors: Byron A. Alcorn, Robert W. Cherry, Mark D. Coleman, Brian D. Rauchfuss, Gary L. Taylor