Patents by Inventor Brian Doyle

Brian Doyle has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SYSTEMS, METHODS AND INTERFACES FOR EVALUATING AN ONLINE ENTITY PRESENCE
    Publication number: 20140095598
    Abstract: A method for evaluating an online entity presence includes receiving a set of social media information for at least one entity and calculating a social media measurement where the social media measurement is associated with the set of social media information. The method further includes receiving a set of online profile information for the at least one entity, the set of online profile information being associated with one or more non-social media online profiles, and calculating an online profile measurement wherein the online profile measurement is associated with the set of online profile information. The method further includes calculating a reach value, the reach value being associated with the social media measurement and the online profile measurement and providing a reach score to a user where the reach score associated with the reach value.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Applicant: WEST SERVICES INC.
    Inventors: JILL SCHORNACK, Eric Iverson, Brian Doyle, Aaron Hareid
  • PERPENDICULAR MTJ STACKS WITH MAGNETIC ANISOTROPY ENHANCING LAYER AND CRYSTALLIZATION BARRIER LAYER
    Publication number: 20140084398
    Abstract: Magnetic tunnel junctions (MTJ) suitable for spin transfer torque memory (STTM) devices, include perpendicular magnetic layers and one or more anisotropy enhancing layer(s) separated from a free magnetic layer by a crystallization barrier layer. In embodiments, an anisotropy enhancing layer improves perpendicular orientation of the free magnetic layer while the crystallization barrier improves tunnel magnetoresistance (TMR) ratio with better alignment of crystalline texture of the free magnetic layer with that of a tunneling layer.
    Type: Application
    Filed: September 26, 2012
    Publication date: March 27, 2014
    Inventors: Kaan OGUZ, Mark L. DOCZY, Brian DOYLE, Uday SHAH, David L. KENCKE, Roksana GOLIZADEH MOJARAD, Robert S. CHAU
  • Reducing moirĂ© patterns
    Patent number: 8675986
    Abstract: Among other disclosed subject matter, a computer-implemented method includes receiving illustrated content. The illustrated content includes half-tone content. The method includes blurring at least part of the illustrated content. The blurring is performed according to a blur radius. The method includes downscaling the blurred illustrated content to an output size.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: March 18, 2014
    Assignee: Hachette Book Group, Inc.
    Inventors: Brian Doyle, Ralph Munsen, Eric Cole, James Bean
  • Apparatus for improving multi-gate device performance
    Patent number: 8618609
    Abstract: Embodiments of an apparatus and methods for improving multi-gate device performance are generally described herein. Other embodiments may be described and claimed.
    Type: Grant
    Filed: October 1, 2010
    Date of Patent: December 31, 2013
    Assignee: Intel Corporation
    Inventors: Brian Doyle, Titash Rakshit, Jack Kavalieros
  • METHOD OF PATTERNING A METAL ON A VERTICAL SIDEWALL OF AN EXCAVATED FEATURE, METHOD OF FORMING AN EMBEDDED MIM CAPACITOR USING SAME, AND EMBEDDED MEMORY DEVICE PRODUCED THEREBY
    Publication number: 20130234290
    Abstract: A method of patterning a metal (141, 341, 841) on a vertical sidewall (132, 332, 832) of an excavated feature (130, 330, 830) includes placing a material (350) in the excavated feature such that a portion (435) of the metal is exposed in the excavated feature above the material, etching the exposed portion of the metal away from the vertical sidewall using a first wet etch chemistry, and removing the material from the excavated feature by etching it away using a second wet etch chemistry. The described method may be used to produce a MIM capacitor (800) suitable for an eDRAM device.
    Type: Application
    Filed: April 23, 2013
    Publication date: September 12, 2013
    Inventors: Steven Keating, Nick Lindert, Nadia Rahhal-Orabi, Brian Doyle, Satyarth Suri, Swaminathan Sivakumar, Lana Jong, Lin Sha
  • Nonplanar device with thinned lower body portion and method of fabrication
    Patent number: 8502351
    Abstract: A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: August 6, 2013
    Assignee: Intel Corporation
    Inventors: Uday Shah, Brian Doyle, Justin K. Brask, Robert S. Chau, Thomas A. Letson
  • DEVICE AND METHOD FOR PERFORMING EXERCISES USING A FREELY ROTATING BALL
    Publication number: 20130184131
    Abstract: Exemplary embodiments of an exercise apparatus and its method of use are provided. An exercise apparatus can be provided having a resilient ball configured to support a weight of a user performing exercises thereon, and a shell member configured to cover at least an upper portion of the resilient ball. The shell member can have an inner surface conforming to an outer surface of the resilient ball. A toroidal member can be provided that can be attached to the shell member and can surround a portion of the resilient ball.
    Type: Application
    Filed: June 21, 2012
    Publication date: July 18, 2013
    Inventor: Brian Doyle
  • REDUCING MOIRÉ PATTERNS
    Publication number: 20130142450
    Abstract: Among other disclosed subject matter, a computer-implemented method includes receiving illustrated content. The illustrated content includes half-tone content. The method includes blurring at least part of the illustrated content. The blurring is performed according to a blur radius. The method includes downscaling the blurred illustrated content to an output size.
    Type: Application
    Filed: December 1, 2011
    Publication date: June 6, 2013
    Inventors: Brian Doyle, Ralph Munsen, Eric Cole, James Bean
  • Embedded memory device having MIM capacitor formed in excavated structure
    Patent number: 8441057
    Abstract: A method of patterning a metal (141, 341, 841) on a vertical sidewall (132, 332, 832) of an excavated feature (130, 330, 830) includes placing a material (350) in the excavated feature such that a portion (435) of the metal is exposed in the excavated feature above the material, etching the exposed portion of the metal away from the vertical sidewall using a first wet etch chemistry, and removing the material from the excavated feature by etching it away using a second wet etch chemistry. The described method may be used to produce a MIM capacitor (800) suitable for an eDRAM device.
    Type: Grant
    Filed: February 16, 2011
    Date of Patent: May 14, 2013
    Assignee: Intel Corporation
    Inventors: Steven J. Keating, Nick Lindert, Nadia Rahhal-Orabi, Brian Doyle, Satyarth Suri, Swaminathan Sivakumar, Lana Jong, Lin Sha
  • Methods of forming nanodots using spacer patterning techniques and structures formed thereby
    Patent number: 8388854
    Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a first block on a nanodot material, forming a first spacer on the first block, removing the first block to form a free standing spacer, removing exposed portions of the nanodot material and then the free standing spacer to form nanowires, forming a second block at an angle to a length of the nanowires, forming a second spacer on the second block, forming a second free standing spacer on the nanowires by removing the second block, and removing exposed portions of the nanowires and then the second free standing spacer to form an ordered array of nanodots.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: March 5, 2013
    Assignee: Intel Corporation
    Inventors: Brian Doyle, Been-Yih Jin, Jack Kavalieros, Robert Chau
  • Trigate static random-access memory with independent source and drain engineering, and devices made therefrom
    Patent number: 8361871
    Abstract: A static random-access memory circuit includes at least one access device including source and drain sections for a pass region, at least one pull-up device and at least one pull-down device including source-and-drain sections for a pull-down region. The static random-access memory circuit is configured with external resistivity (Rext) for the pull-down region to be lower than Rext for the pass region. Processes of achieving the static random-access memory circuit include source-and-drain epitaxy.
    Type: Grant
    Filed: December 24, 2008
    Date of Patent: January 29, 2013
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Willy Rachmady, Brian Doyle, Robert S. Chau
  • TRIGATE STATIC RANDOM-ACCESS MEMORY WITH INDEPENDENT SOURCE AND DRAIN ENGINEERING, AND DEVICES MADE THEREFROM
    Publication number: 20120292709
    Abstract: A static random-access memory circuit includes at least one access device including source and drain sections for a pass region, at least one pull-up device and at least one pull-down device including source-and-drain sections for a pull-down region. The static random-access memory circuit is configured with external resistivity (Rext) for the pull-down region to be lower than Rext for the pass region. Processes of achieving the static random-access memory circuit include source-and-drain epitaxy.
    Type: Application
    Filed: July 31, 2012
    Publication date: November 22, 2012
    Inventors: Ravi Pillarisetty, Willy Rachmady, Brian Doyle, Robert S. Chau
  • Method to introduce uniaxial strain in multigate nanoscale transistors by self aligned SI to SIGE conversion processes and structures formed thereby
    Patent number: 8288233
    Abstract: Methods of forming a microelectronic structure are described. Embodiments of those methods may include providing a gate electrode comprising a top surface and first and second laterally opposite sidewalls, wherein a hard mask is disposed on the top surface, a source drain region disposed on opposite sides of the gate electrode, and a spacer disposed on the first and second laterally opposed sidewalls of the gate electrode, forming a silicon germanium layer on exposed portions of the top surface and the first and second laterally opposite sidewalls of the source drain region and then oxidizing a portion of the silicon germanium layer, wherein a germanium portion of the silicon germanium layer is forced down into the source drain region to convert a silicon portion of the source drain region into a silicon germanium portion of the source drain region.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: October 16, 2012
    Assignee: Intel Corporation
    Inventors: Been-Yih Jin, Brian Doyle, Jack Kavalieros, Suman Datta
  • NONPLANAR DEVICE WITH THINNED LOWER BODY PORTION AND METHOD OF FABRICATION
    Publication number: 20120012934
    Abstract: A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.
    Type: Application
    Filed: September 23, 2011
    Publication date: January 19, 2012
    Inventors: Uday Shah, Brian Doyle, Justin K. Brask, Robert S. Chau, Thomas A. Letson
  • High mobility tri-gate devices and methods of fabrication
    Patent number: 8084818
    Abstract: A high mobility semiconductor assembly. In one exemplary aspect, the high mobility semiconductor assembly includes a first substrate having a first reference orientation located at a <110> crystal plane location on the first substrate and a second substrate formed on top of the first substrate. The second substrate has a second reference orientation located at a <100> crystal plane location on the second substrate, wherein the first reference orientation is aligned with the second reference orientation. In another exemplary aspect, the second substrate has a second reference orientation located at a <110> crystal plane location on the second substrate, wherein the second substrate is formed over the first substrate with the second reference orientation being offset to the first reference orientation by about 45 degrees.
    Type: Grant
    Filed: January 12, 2006
    Date of Patent: December 27, 2011
    Assignee: Intel Corporation
    Inventors: Mohamad A. Shaheen, Brian Doyle, Suman Dutta, Robert S. Chau, Peter Tolchinksy
  • Nonplanar device with thinned lower body portion and method of fabrication
    Patent number: 8067818
    Abstract: A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.
    Type: Grant
    Filed: November 24, 2010
    Date of Patent: November 29, 2011
    Assignee: Intel Corporation
    Inventors: Uday Shah, Brian Doyle, Justin K. Brask, Robert S. Chau, Thomas A. Letson
  • Common plate capacitor array connections, and processes of making same
    Patent number: 7981756
    Abstract: A process of forming a semiconductive capacitor device for a memory circuit includes forming a first capacitor cell recess and a second capacitor cell recess that are spaced apart by a capacitor cell boundary of a first height. The process includes lowering the first height of the capacitor cell boundary to a second height. A common plate capacitor bridges between the first recess and the second recess over the boundary above the second height and below the first height.
    Type: Grant
    Filed: December 22, 2008
    Date of Patent: July 19, 2011
    Assignee: Intel Corporation
    Inventors: Nick Lindert, Brian Doyle, Dinesh Somasekhar, Christopher J. Jezewski, Swaminathan Sivakumar, Kevin Zhang, Stephen Wu
  • METHOD OF PATTERNING A METAL ON A VERTICAL SIDEWALL OF AN EXCAVATED FEATURE, METHOD OF FORMING AN EMBEDDED MIM CAPACITOR USING SAME, AND EMBEDDED MEMORY DEVICE PRODUCED THEREBY
    Publication number: 20110134583
    Abstract: A method of patterning a metal (141, 341, 841) on a vertical sidewall (132, 332, 832) of an excavated feature (130, 330, 830) includes placing a material (350) in the excavated feature such that a portion (435) of the metal is exposed in the excavated feature above the material, etching the exposed portion of the metal away from the vertical sidewall using a first wet etch chemistry, and removing the material from the excavated feature by etching it away using a second wet etch chemistry. The described method may be used to produce a MIM capacitor (800) suitable for an eDRAM device.
    Type: Application
    Filed: February 16, 2011
    Publication date: June 9, 2011
    Inventors: Steve J. Keating, Nick Lindert, Nadia Rahhal-Orabi, Brian Doyle, Satyarth Suri, Swaminathan Sivakumar, Lana Jong, Lin Sha
  • Metalgate electrode for PMOS transistor
    Patent number: 7936025
    Abstract: Described is a CMOS transistor structure with a multi-layered gate electrode structure and a method of fabrication. The gate electrode structure has a three-layered metallic gate electrode and a polysilicon layer. The first metallic layer acts as a barrier to prevent the second metallic layer from reacting with an underlying dielectric. The second metallic layer acts to set the work function of the gate electrode structure. The third metallic layer acts as a barrier to prevent the second metallic layer from reacting with the polysilicon layer.
    Type: Grant
    Filed: September 20, 2005
    Date of Patent: May 3, 2011
    Assignee: Intel Corporation
    Inventors: Robert Chau, Mark Doczy, Brian Doyle, Jack Kavalieros
  • Method of patterning a metal on a vertical sidewall of an excavated feature, method of forming an embedded MIM capacitor using same, and embedded memory device produced thereby
    Patent number: 7927959
    Abstract: A method of patterning a metal (141, 341, 841) on a vertical sidewall (132, 332, 832) of an excavated feature (130, 330, 830) includes placing a material (350) in the excavated feature such that a portion (435) of the metal is exposed in the excavated feature above the material, etching the exposed portion of the metal away from the vertical sidewall using a first wet etch chemistry, and removing the material from the excavated feature by etching it away using a second wet etch chemistry. The described method may be used to produce a MIM capacitor (800) suitable for an eDRAM device.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: April 19, 2011
    Assignee: Intel Corporation
    Inventors: Steven J. Keating, Nick Lindert, Nadia Rahhal-Orabi, Brian Doyle, Satyarth Suri, Swaminathan Sivakumar, Lana Jong, Lin Sha