Patents by Inventor Brian DREIBELBIS
Brian DREIBELBIS has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9378328Abstract: Systems and methods for modeling multi-patterning variability with statistical timing analysis during IC fabrication are described. The method may be provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to define at least one source of variation in an integrated circuit design. The programming instructions further operable to model the at least one source of variation for at least two patterns in at least one level of the integrated circuit design as at least two sources of variability respectively.Type: GrantFiled: November 25, 2014Date of Patent: June 28, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Nathan Buck, Brian Dreibelbis, John P. Dubuque, Eric A. Foreman, Peter A. Habitz, David J. Hathaway, Jeffrey G. Hemmett, Natesan Venkateswaran, Chandramouli Visweswariah, Vladimir Zolotov
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Patent number: 9348962Abstract: Systems and methods for avoiding restrictions on cell placement in a hierarchical design of integrated circuits with multi-patterning requirements are described. The method may be provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to assign a color to each pattern shape in a first cell, assign a color to each pattern shape in a second cell, characterize quantities of interest for each pattern shape in the first cell, determine that the colors assigned in the first cell are all one to one mappable to the colors assigned in the second cells, characterize quantities of interest for each pattern shape in the second cell using the quantities of interest characterized for the first cell, and model the quantities of interest for the first cell and the second cell.Type: GrantFiled: August 19, 2014Date of Patent: May 24, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Nathan Buck, Brian Dreibelbis, John P. Dubuque, Eric A. Foreman, David J. Hathaway, Jeffrey G. Hemmett, Natesan Venkateswaran, Chandramouli Visweswariah, Vladimir Zolotov
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Patent number: 9171124Abstract: Systems and methods are provided for extracting parasitics in a design of an integrated circuit with multi-patterning requirements. The method includes determining resistance solutions and capacitance solutions. The method further includes performing parasitic extraction of the resistance solutions and the capacitance solutions to generate mean values for the resistance solutions and the capacitance solutions. The method further includes capturing a multi-patterning source of variation for each of the resistance solutions and the capacitance solutions during the parasitic extraction. The method further includes determining a sensitivity for each captured source of variation to a respective vector of parameters. The method further includes determining statistical parasitics by multiplying each of the resistance solutions and the capacitance solutions by the determined sensitivity for each respective captured source of variation.Type: GrantFiled: December 23, 2013Date of Patent: October 27, 2015Assignee: GLOBALFOUNDRIES U.S. 2 LLCInventors: Nathan Buck, Brian Dreibelbis, John P. Dubuque, Eric A. Foreman, Peter A. Habitz, David J. Hathaway, Jeffrey G. Hemmett, Natesan Venkateswaran, Chandramouli Visweswariah, Vladimir Zolotov
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Publication number: 20150082260Abstract: Systems and methods for modeling multi-patterning variability with statistical timing analysis during IC fabrication are described. The method may be provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to define at least one source of variation in an integrated circuit design. The programming instructions further operable to model the at least one source of variation for at least two patterns in at least one level of the integrated circuit design as at least two sources of variability respectively.Type: ApplicationFiled: November 25, 2014Publication date: March 19, 2015Inventors: Nathan BUCK, Brian DREIBELBIS, John P. DUBUQUE, Eric A. FOREMAN, Peter A. HABITZ, David J. HATHAWAY, Jeffrey G. HEMMETT, Natesan VENKATESWARAN, Chandramouli VISWESWARIAH, Vladimir ZOLOTOV
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Patent number: 8949765Abstract: Systems and methods for modeling multi-patterning variability with statistical timing analysis during IC fabrication are described. The method may be provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to define at least one source of variation in an integrated circuit design. The programming instructions further operable to model the at least one source of variation for at least two patterns in at least one level of the integrated circuit design as at least two sources of variability respectively.Type: GrantFiled: December 23, 2013Date of Patent: February 3, 2015Assignee: International Business Machines CorporationInventors: Nathan Buck, Brian Dreibelbis, John P. Dubuque, Eric A. Foreman, Peter A. Habitz, David J. Hathaway, Jeffrey G. Hemmett, Natesan Venkateswaran, Chandramouli Visweswariah, Vladimir Zolotov
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Publication number: 20140359547Abstract: Systems and methods for avoiding restrictions on cell placement in a hierarchical design of integrated circuits with multi-patterning requirements are described. The method may be provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to assign a color to each pattern shape in a first cell, assign a color to each pattern shape in a second cell, characterize quantities of interest for each pattern shape in the first cell, determine that the colors assigned in the first cell are all one to one mappable to the colors assigned in the second cells, characterize quantities of interest for each pattern shape in the second cell using the quantities of interest characterized for the first cell, and model the quantities of interest for the first cell and the second cell.Type: ApplicationFiled: August 19, 2014Publication date: December 4, 2014Inventors: Nathan BUCK, Brian DREIBELBIS, John P. DUBUQUE, Eric A. FOREMAN, David J. HATHAWAY, Jeffrey G. HEMMETT, Natesan VENKATESWARAN, Chandramouli VISWESWARIAH, Vladimir ZOLOTOV
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Publication number: 20140298280Abstract: Systems and methods for performing static timing analysis during IC design. A method is provided that includes obtaining canonical input data. The method further includes calculating at least one input condition identifier based on the canonical input data. The method further includes comparing the at least one input condition identifier to a table of values. The method further includes that when a match exists between the at least one input condition identifier and at least one value within the table of values, retrieving previously calculated timing data associated with the at least one value, and applying the previously calculated timing data in a timing model for a design under timing analysis.Type: ApplicationFiled: April 2, 2013Publication date: October 2, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brian DREIBELBIS, John P. DUBUQUE, Eric A. FOREMAN, David J. HATHAWAY, Jeffrey G. HEMMETT, Natesan VENKATESWARAN, Chandramouli VISWESWARIAH, Vladimir ZOLOTOV
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Patent number: 8850378Abstract: Systems and methods for avoiding restrictions on cell placement in a hierarchical design of integrated circuits with multi-patterning requirements are described. The method may be provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to assign a color to each pattern shape in a first cell, assign a color to each pattern shape in a second cell, characterize quantities of interest for each pattern shape in the first cell, determine that the colors assigned in the first cell are all one to one mappable to the colors assigned in the second cells, characterize quantities of interest for each pattern shape in the second cell using the quantities of interest characterized for the first cell, and model the quantities of interest for the first cell and the second cell.Type: GrantFiled: October 31, 2012Date of Patent: September 30, 2014Assignee: International Business Machines CorporationInventors: Nathan Buck, Brian Dreibelbis, John P. Dubuque, Eric A. Foreman, Peter A. Habitz, David J. Hathaway, Jeffrey G. Hemmett, Natesan Venkateswaran, Chandramouli Visweswariah, Vladimir Zolotov
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Patent number: 8839167Abstract: Systems and methods for performing static timing analysis during IC design. A method is provided that includes obtaining canonical input data. The method further includes calculating at least one input condition identifier based on the canonical input data. The method further includes comparing the at least one input condition identifier to a table of values. The method further includes that when a match exists between the at least one input condition identifier and at least one value within the table of values, retrieving previously calculated timing data associated with the at least one value, and applying the previously calculated timing data in a timing model for a design under timing analysis.Type: GrantFiled: April 2, 2013Date of Patent: September 16, 2014Assignee: International Business Machines CorporationInventors: Brian Dreibelbis, John P. Dubuque, Eric A. Foreman, David J. Hathaway, Jeffrey G. Hemmett, Natesan Venkateswaran, Chandramouli Visweswariah, Vladimir Zolotov
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Patent number: 8806402Abstract: Systems and methods for modeling multi-patterning variability with statistical timing analysis during IC fabrication are described. The method may be provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to define at least one source of variation in an integrated circuit design. The programming instructions further operable to model the at least one source of variation for at least two patterns in at least one level of the integrated circuit design as at least two sources of variability respectively.Type: GrantFiled: October 31, 2012Date of Patent: August 12, 2014Assignee: International Business Machines CorporationInventors: Nathan Buck, Brian Dreibelbis, John P. Dubuque, Eric A. Foreman, Peter A. Habitz, David J. Hathaway, Jeffrey G. Hemmett, Natesan Venkateswaran, Chandramouli Visweswariah, Vladimir Zolotov
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Patent number: 8769452Abstract: Systems and methods are provided for extracting parasitics in a design of an integrated circuit with multi-patterning requirements. The method includes determining resistance solutions and capacitance solutions. The method further includes performing parasitic extraction of the resistance solutions and the capacitance solutions to generate mean values for the resistance solutions and the capacitance solutions. The method further includes capturing a multi-patterning source of variation for each of the resistance solutions and the capacitance solutions during the parasitic extraction. The method further includes determining a sensitivity for each captured source of variation to a respective vector of parameters. The method further includes determining statistical parasitics by multiplying each of the resistance solutions and the capacitance solutions by the determined sensitivity for each respective captured source of variation.Type: GrantFiled: October 31, 2012Date of Patent: July 1, 2014Assignee: International Business Machines CorporationInventors: Nathan Buck, Brian Dreibelbis, John P. Dubuque, Eric A. Foreman, Peter A. Habitz, David J. Hathaway, Jeffrey G. Hemmett, Natesan Venkateswaran, Chandramouli Visweswariah, Vladimir Zolotov
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Publication number: 20140173543Abstract: Systems and methods are provided for extracting parasitics in a design of an integrated circuit with multi-patterning requirements. The method includes determining resistance solutions and capacitance solutions. The method further includes performing parasitic extraction of the resistance solutions and the capacitance solutions to generate mean values for the resistance solutions and the capacitance solutions. The method further includes capturing a multi-patterning source of variation for each of the resistance solutions and the capacitance solutions during the parasitic extraction. The method further includes determining a sensitivity for each captured source of variation to a respective vector of parameters. The method further includes determining statistical parasitics by multiplying each of the resistance solutions and the capacitance solutions by the determined sensitivity for each respective captured source of variation.Type: ApplicationFiled: December 23, 2013Publication date: June 19, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Nathan BUCK, Brian DREIBELBIS, John P. DUBUQUE, Eric A. FOREMAN, Peter A. HABITZ, David J. HATHAWAY, Jeffrey G. HEMMETT, Natesan VENKATESWARAN, Chandramouli VISWESWARIAH, Vladimir ZOLOTOV
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Publication number: 20140123095Abstract: Systems and methods for modeling multi-patterning variability with statistical timing analysis during IC fabrication are described. The method may be provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to define at least one source of variation in an integrated circuit design. The programming instructions further operable to model the at least one source of variation for at least two patterns in at least one level of the integrated circuit design as at least two sources of variability respectively.Type: ApplicationFiled: December 23, 2013Publication date: May 1, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Nathan BUCK, Brian DREIBELBIS, John P. DUBUQUE, Eric A. FOREMAN, Peter A. HABITZ, David J. HATHAWAY, Jeffrey G. HEMMETT, Natesan VENKATESWARAN, Chandramouli VISWESWARIAH, Vladimir ZOLOTOV
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Publication number: 20140123089Abstract: Systems and methods for modeling multi-patterning variability with statistical timing analysis during IC fabrication are described. The method may be provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to define at least one source of variation in an integrated circuit design. The programming instructions further operable to model the at least one source of variation for at least two patterns in at least one level of the integrated circuit design as at least two sources of variability respectively.Type: ApplicationFiled: October 31, 2012Publication date: May 1, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Nathan BUCK, Brian DREIBELBIS, John P. DUBUQUE, Eric A. FOREMAN, Peter A. HABITZ, David J. HATHAWAY, Jeffrey G. HEMMETT, Natesan VENKATESWARAN, Chandramouli VISWESWARIAH, Vladimir ZOLOTOV
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Publication number: 20140123086Abstract: Systems and methods are provided for extracting parasitics in a design of an integrated circuit with multi-patterning requirements. The method includes determining resistance solutions and capacitance solutions. The method further includes performing parasitic extraction of the resistance solutions and the capacitance solutions to generate mean values for the resistance solutions and the capacitance solutions. The method further includes capturing a multi-patterning source of variation for each of the resistance solutions and the capacitance solutions during the parasitic extraction. The method further includes determining a sensitivity for each captured source of variation to a respective vector of parameters. The method further includes determining statistical parasitics by multiplying each of the resistance solutions and the capacitance solutions by the determined sensitivity for each respective captured source of variation.Type: ApplicationFiled: October 31, 2012Publication date: May 1, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Nathan BUCK, Brian DREIBELBIS, John P. DUBUQUE, Eric A. FOREMAN, Peter A. HABITZ, David J. HATHAWAY, Jeffrey G. HEMMETT, Natesan VENKATESWARAN, Chandramouli VISWESWARIAH, Vladimir ZOLOTOV
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Patent number: 8560989Abstract: Systems and methods for statistical clock cycle computation and closing timing of an integrated circuit design to a maximum clock cycle or period. The method includes loading a design and timing model for at least one circuit path of an integrated circuit or a region of the integrated circuit into a computing device. The method further includes performing a statistical static timing analysis (SSTA) of the at least one circuit path using the loaded design and timing model to obtain slack canonical data. The method further includes calculating a maximum circuit clock cycle for the integrated circuit or the specified region of the integrated circuit in linear canonical form based upon the slack canonical data obtained from the SSTA.Type: GrantFiled: December 6, 2011Date of Patent: October 15, 2013Assignee: International Business Machines CorporationInventors: Nathan Buck, Brian Dreibelbis, John P. Dubuque, Eric A. Foreman, James C. Gregerson, Peter A. Habitz, Jeffrey G. Hemmett, Debjit Sinha, Natesan Venkateswaran, Chandramouli Visweswariah, Michael H. Wood, Vladimir Zolotov
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Publication number: 20130145333Abstract: Systems and methods for statistical clock cycle computation and closing timing of an integrated circuit design to a maximum clock cycle or period. The method includes loading a design and timing model for at least one circuit path of an integrated circuit or a region of the integrated circuit into a computing device. The method further includes performing a statistical static timing analysis (SSTA) of the at least one circuit path using the loaded design and timing model to obtain slack canonical data. The method further includes calculating a maximum circuit clock cycle for the integrated circuit or the specified region of the integrated circuit in linear canonical form based upon the slack canonical data obtained from the SSTA.Type: ApplicationFiled: December 6, 2011Publication date: June 6, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Nathan BUCK, Brian DREIBELBIS, John P. DUBUQUE, Eric A. FOREMAN, James C. GREGERSON, Peter A. HABITZ, Jeffrey G. HEMMETT, Debjit SINHA, Natesan VENKATESWARAN, Chandramouli VISWESWARIAH, Michael H. WOOD, Vladimir ZOLOTOV