Patents by Inventor Brian E. Mastenbrook

Brian E. Mastenbrook has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140064260
    Abstract: Methods and systems are disclosed for a first wireless device to select a wireless network connection to a second wireless device. The wireless network may be a wireless local area network (WLAN), such as a Wi-Fi network. To make its selection, the first wireless device detects a beacon signal transmitted from the second wireless device. The beacon signal including a media access control (MAC) address. The first device then applies a set of programmable rules to at least a portion of the MAC address, and selects the second wireless device based on the application of the rules. The rules may also/alternatively be applied to parameters, for example, sensory inputs, such as time and date, temperature, light intensity or user actions (e.g., screen swipes, button pushes), that are immediate or recorded in a database, whereby certain patterns are matched in order to make the selection.
    Type: Application
    Filed: August 30, 2013
    Publication date: March 6, 2014
    Inventors: Brian E. Mastenbrook, Matthew H. Klapman
  • Publication number: 20140059316
    Abstract: A graph access device and block access device can simultaneously access a memory pool shared between the devices. The memory pool may include one or more memory arrays accessed as a single logical memory. The block access device accesses the memory pool as a flat array of memory blocks, and the graph access device accesses the memory pool as hierarchical file system. The simultaneous access is accomplished by monitoring one or more memory block access operations performed by the block access device, while it is accessing the memory pool. The block access operations are translated into a graph data structure including a plurality of pointers mapping the memory pool to the hierarchical file system. A processor regulates access to the memory pool, and is configured to permit the graph access device to access the memory pool concurrently with the block access device, in accordance with the graph data structure.
    Type: Application
    Filed: August 30, 2013
    Publication date: February 27, 2014
    Applicant: WEARABLE, INC.
    Inventors: Matthew H. Klapman, Brian E. Mastenbrook
  • Patent number: 8527719
    Abstract: A graph access device and block access device can simultaneously access a memory pool shared between the devices. The memory pool may include one or more memory arrays accessed as a single logical memory. The block access device accesses the memory pool as a flat array of memory blocks, and the graph access device accesses the memory pool as hierarchical file system. The simultaneous access is accomplished by monitoring one or more memory block access operations performed by the block access device, while it is accessing the memory pool. The block access operations are translated into a graph data structure including a plurality of pointers mapping the memory pool to the hierarchical file system. A processor regulates access to the memory pool, and is configured to permit the graph access device to access the memory pool concurrently with the block access device, in accordance with the graph data structure.
    Type: Grant
    Filed: October 26, 2010
    Date of Patent: September 3, 2013
    Inventors: Matthew H. Klapman, Brian E. Mastenbrook
  • Publication number: 20110113210
    Abstract: A graph access device and block access device can simultaneously access a memory pool shared between the devices. The memory pool may include one or more memory arrays accessed as a single logical memory. The block access device accesses the memory pool as a flat array of memory blocks, and the graph access device accesses the memory pool as hierarchical file system. The simultaneous access is accomplished by monitoring one or more memory block access operations performed by the block access device, while it is accessing the memory pool. The block access operations are translated into a graph data structure including a plurality of pointers mapping the memory pool to the hierarchical file system. A processor regulates access to the memory pool, and is configured to permit the graph access device to access the memory pool concurrently with the block access device, in accordance with the graph data structure.
    Type: Application
    Filed: October 26, 2010
    Publication date: May 12, 2011
    Inventors: Matthew H. Klapman, Brian E. Mastenbrook