Patents by Inventor Brian G. Anthony

Brian G. Anthony has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6713381
    Abstract: An interconnect overlies a semiconductor device substrate (10). In one embodiment, a conductive barrier layer overlies a portion of the interconnect, a passivation layer (92) overlies the conductive barrier layer and the passivation layer (92) has an opening that exposes portions of the conductive barrier layer (82). In an alternate embodiment a passivation layer (22) overlies the interconnect, the passivation layer (22) has an opening (24) that exposes the interconnect and a conductive barrier layer (32) overlies the interconnect within the opening (24).
    Type: Grant
    Filed: January 18, 2002
    Date of Patent: March 30, 2004
    Assignee: Motorola, Inc.
    Inventors: Alexander L. Barr, Suresh Venkatesan, David B. Clegg, Rebecca G. Cole, Olubunmi Adetutu, Stuart E. Greer, Brian G. Anthony, Ramnath Venkatraman, Gregor Braeckelmann, Douglas M. Reber, Stephen R. Crown
  • Patent number: 6573173
    Abstract: A copper interconnect polishing process begins by polishing (17) a bulk thickness of copper (63) using a first platen. A second platen is then used to remove (19) a thin remaining interfacial copper layer to expose a barrier film (61). Computer control (21) monitors polish times of the first and second platen and adjusts these times to improve wafer throughput. One or more platens and/or the wafer is rinsed (20) between the interfacial copper polish and the barrier polish to reduce slurry cross contamination. A third platen and slurry is then used to polish away exposed portions of the barrier (61) to complete polishing of the copper interconnect structure. A holding tank that contains anti-corrosive fluid is used to queue the wafers until subsequent scrubbing operations (25). A scrubbing operation (25) that is substantially void of light is used to reduce photovoltaic induced corrosion of copper in the drying chamber of the scubber.
    Type: Grant
    Filed: June 20, 2002
    Date of Patent: June 3, 2003
    Assignee: Motorola, Inc.
    Inventors: Janos Farkas, Brian G. Anthony, Abbas Guvenilir, Mohammed Rabiul Islam, Venkat Kolagunta, John Mendonca, Rajesh Tiwari, Suresh Venkatesan
  • Publication number: 20020151167
    Abstract: A copper interconnect polishing process begins by polishing (17) a bulk thickness of copper (63) using a first platen. A second platen is then used to remove (19) a thin remaining interfacial copper layer to expose a barrier film (61). Computer control (21) monitors polish times of the first and second platen and adjusts these times to improve wafer throughput. One or more platens and/or the wafer is rinsed (20) between the interfacial copper polish and the barrier polish to reduce slurry cross contamination. A third platen and slurry is then used to polish away exposed portions of the barrier (61) to complete polishing of the copper interconnect structure. A holding tank that contains anti-corrosive fluid is used to queue the wafers until subsequent scrubbing operations (25). A scrubbing operation (25) that is substantially void of light is used to reduce photovoltaic induced corrosion of copper in the drying chamber of the scubber.
    Type: Application
    Filed: June 20, 2002
    Publication date: October 17, 2002
    Inventors: Janos Farkas, Brian G. Anthony, Abbas Guvenilir, Mohammed Rabiul Islam, Venkat Kolagunta, John Mendonca, Rajesh Tiwari, Suresh Venkatesan
  • Patent number: 6451181
    Abstract: A method for forming an improved copper inlaid interconnect (FIG. 11) begins by performing an RF preclean operation (408) on the inlaid structure in a chamber (10). The RF preclean rounds corners (210a and 206a) of the structure to reduce voiding and improve step coverage while not significantly removing copper atoms from the underlying exposed copper interconnects surfaces (202a). A tantalum barrier (220) is then deposited where one portion of the tantalum barrier is more tensile than another portion of the tantalum barrier. After formation of the barrier layer (220), a copper seed layer (222) is formed over a top of the barrier layer. The copper layer is formed while clamping the wafer with an improved clamp (85) which reduces copper peeling and contamination at wafer edges. Copper electroplating and chemical mechanical polishing (CMP) processes are then used to complete the copper interconnect structure.
    Type: Grant
    Filed: March 2, 1999
    Date of Patent: September 17, 2002
    Assignee: Motorola, Inc.
    Inventors: Dean J. Denning, Sam S. Garcia, Bradley P. Smith, Daniel J. Loop, Gregory Norman Hamilton, Md. Rabiul Islam, Brian G. Anthony
  • Patent number: 6444569
    Abstract: A copper interconnect polishing process begins by polishing (17) a bulk thickness of copper (63) using a first platen. A second platen is then used to remove (19) a thin remaining interfacial copper layer to expose a barrier film (61). Computer control (21) monitors polish times of the first and second platen and adjusts these times to improve wafer throughput. One or more platens and/or the wafer is rinsed (20) between the interfacial copper polish and the barrier polish to reduce slurry cross contamination. A third platen and slurry is then used to polish away exposed portions of the barrier (61) to complete polishing of the copper interconnect structure. A holding tank that contains anti-corrosive fluid is used to queue the wafers until subsequent scrubbing operations (25). A scrubbing operation (25) that is substantially void of light is used to reduce photovoltaic induced corrosion of copper in the drying chamber of the scubber.
    Type: Grant
    Filed: April 16, 2001
    Date of Patent: September 3, 2002
    Assignee: Motorola, Inc.
    Inventors: Janos Farkas, Brian G. Anthony, Abbas Guvenilir, Mohammed Rabiul Islam, Venkat Kolagunta, John Mendonca, Rajesh Tiwari, Suresh Venkatesan
  • Publication number: 20020092763
    Abstract: A method for forming an improved copper inlaid interconnect (FIG. 11) begins by performing an RF preclean operation (408) on the inlaid structure in a chamber (10). The RF preclean rounds corners (210a and 206a) of the structure to reduce voiding and improve step coverage while not significantly removing copper atoms from the underlying exposed copper interconnects surfaces (202a). A tantalum barrier (220) is then deposited where one portion of the tantalum barrier is more tensile than another portion of the tantalum barrier. After formation of the barrier layer (220), a copper seed layer (222) is formed over a top of the barrier layer. The copper layer is formed while clamping the wafer with an improved clamp (85) which reduces copper peeling and contamination at wafer edges. Copper electroplating and chemical mechanical polishing (CMP) processes are then used to complete the copper interconnect structure.
    Type: Application
    Filed: February 22, 2002
    Publication date: July 18, 2002
    Inventors: Dean J. Denning, Sam S. Garcia, Bradley P. Smith, Daniel J. Loop, Gregory Norman Hamilton, Md. Rabiul Islam, Brian G. Anthony
  • Publication number: 20020093098
    Abstract: An interconnect overlies a semiconductor device substrate (10). In one embodiment, a conductive barrier layer overlies a portion of the interconnect, a passivation layer (92) overlies the conductive barrier layer and the passivation layer (92) has an opening that exposes portions of the conductive barrier layer (82). In an alternate embodiment a passivation layer (22) overlies the interconnect, the passivation layer (22) has an opening (24) that exposes the interconnect and a conductive barrier layer (32) overlies the interconnect within the opening (24).
    Type: Application
    Filed: January 18, 2002
    Publication date: July 18, 2002
    Inventors: Alexander L. Barr, Suresh Venkatesan, David B. Clegg, Rebecca G. Cole, Olubunmi Adetutu, Stuart E. Greer, Brian G. Anthony, Ramnath Venkatraman, Gregor Braeckelmann, Douglas M. Reber, Stephen R. Crown
  • Publication number: 20020000665
    Abstract: An interconnect overlies a semiconductor device substrate (10). In one embodiment, a conductive barrier layer overlies a portion of the interconnect, a passivation layer (92) overlies the conductive barrier layer and the passivation layer (92) has an opening that exposes portions of the conductive barrier layer (82). In an alternate embodiment a passivation layer (22) overlies the interconnect, the passivation layer (22) has an opening (24) that exposes the interconnect and a conductive barrier layer (32) overlies the interconnect within the opening (24).
    Type: Application
    Filed: April 5, 1999
    Publication date: January 3, 2002
    Inventors: ALEXANDER L. BARR, SURESH VENKATESAN, DAVID B. CLEGG, REBECCA G. COLE, OLUBUNMI ADETUTU, STUART E. GREER, BRIAN G. ANTHONY, RAMNATH VENKATRAMAN, GREGOR BRAECKELMANN, DOUGLAS M. REBER, STEPHEN R. CROWN
  • Publication number: 20010027083
    Abstract: A copper interconnect polishing process begins by polishing (17) a bulk thickness of copper (63) using a first platen. A second platen is then used to remove (19) a thin remaining interfacial copper layer to expose a barrier film (61). Computer control (21) monitors polish times of the first and second platen and adjusts these times to improve wafer throughput. One or more platens and/or the wafer is rinsed (20) between the interfacial copper polish and the barrier polish to reduce slurry cross contamination. A third platen and slurry is then used to polish away exposed portions of the barrier (61) to complete polishing of the copper interconnect structure. A holding tank that contains anti-corrosive fluid is used to queue the wafers until subsequent scrubbing operations (25). A scrubbing operation (25) that is substantially void of light is used to reduce photovoltaic induced corrosion of copper in the drying chamber of the scubber.
    Type: Application
    Filed: April 16, 2001
    Publication date: October 4, 2001
    Inventors: Janos Farkas, Brian G. Anthony, Abbas Guvenilir, Mohammed Rabiul Islam, Venkat Kolagunta, John Mendonca, Rajesh Tiwari, Suresh Venkatesan
  • Patent number: 6274478
    Abstract: A copper interconnect polishing process begins by polishing (17) a bulk thickness of copper (63) using a first platen. A second platen is then used to remove (19) a thin remaining interfacial copper layer to expose a barrier film (61). Computer control (21) monitors polish times of the first and second platen and adjusts these times to improve wafer throughput. One or more platens and/or the wafer is rinsed (20) between the interfacial copper polish and the barrier polish to reduce slurry cross contamination. A third platen and slurry is then used to polish away exposed portions of the barrier (61) to complete polishing of the copper interconnect structure. A holding tank that contains anti-corrosive fluid is used to queue the wafers until subsequent scrubbing operations (25). A scrubbing operation (25) that is substantially void of light is used to reduce photovoltaic induced corrosion of copper in the drying chamber of the scrubber.
    Type: Grant
    Filed: July 13, 1999
    Date of Patent: August 14, 2001
    Assignee: Motorola, Inc.
    Inventors: Janos Farkas, Brian G. Anthony, Abbas Guvenilir, Mohammed Rabiul Islam, Venkat Kolagunta, John Mendonca, Rajesh Tiwari, Suresh Venkatesan