Abstract: A method of manufacturing a vertical bipolar transistor including the steps of: providing a semiconductor substrate including a first region of a first conductivity type; forming an extrinsic base region of a second conductivity type in the surface of the first region, the extrinsic base region generally bounding a portion of the first region; forming by ion implantation a linking region of the second conductivity type in the surface of the bounded portion of the first region so as to electrically link generally opposing edges of the extrinsic base region through the linking region; forming an insulating spacer over the junction between the extrinsic base region and the linking region so as to generally bound a portion of the linking region within the portion of the first region; etching the surface of the bounded portion of the linking region a short distance into the linking region; forming by epitaxial growth a first layer of semiconductor material of the second conductivity type on the etched surface of t

Abstract: A method of manufacturing a vertical bipolar transistor including the steps of: providing a semiconductor substrate including a first region of a first conductivity type; forming an extrinsic base region of a second conductivity type in the surface of the first region, the extrinsic base region generally bounding a portion of the first region; forming by ion implantation a linking region of the second conductivity type in the surface of the bounded portion of the first region so as to electrically link generally opposing edges of the extrinsic base region through the linking region; forming an insulating spacer over the junction between the extrinsic base region and the linking region so as to generally bound a portion of the linking region within the portion of the first region; etching the surface of the bounded portion of the linking region a short distance into the linking region; forming by epitaxial growth a first layer of semiconductor material of the second conductivity type on the etched surface of t

Abstract: A method of fabricating a lateral transistor is provided, including the steps of: providing a body of semiconductor material including a device region of a first conductivity type; patterning the surface of the device region to define a first transistor region; filling the patterned portion of the device region surrounding the first transistor region with an insulating material to a height generally equal to the surface of with first transistor region; removing portions of the insulating material so as to define a pair of trenches generally bounding opposite sides of the first transistor region; filling the pair of trenches with doped conductive material of opposite conductivity type to the first transistor region; and annealing the semiconductor body whereby to form second and third transistor regions of opposite conductivity type to the first transistor region in the opposing sides of the first transistor region.

Abstract: A method of fabricating a lateral transistor is provided, including the steps of: providing a body of semiconductor material including a device region of a first conductivity type; patterning the surface of the device region to define a first transistor region; filling the patterned portion of the device region surrounding the first transistor region with an insulating material to a height generally equal to the surface of with first transistor region; removing portions of the insulating material so as to define a pair of trenches generally bonding opposite sides of the first transistor region; filling the pair of trenches with doped conductive material of opposite conductivity type to the first transistor region; and annealing the semiconductor body whereby to form second and third transistor regions of opposite conductivity type to the first transistor region in the opposing sides of the first transistor region.

Abstract: A method of image transfer transfer into a substrate by reactive ion etch technique is provided. A mask layer on said substrate is formed by a spin-on film which film is comprised of a mixed organo-functional zircoaluminate or zircotitanate material. The film is dried and cured, and thereafter coated with a radiation sensitive resist. The reist is imagewise exposed and developed, which developing preferably also removes the pattern in the mask exposing the substrate. The substrate is then reactive ion etched, the remaining film acting as a barrier material to the etching.

Abstract: An improved plasma reactor for uniformly etching a large number of semiconductor wafers at a reduced plasma potential includes, in one embodiment, a grounded plate mounted intermediate the cathode and the top plate of a reactor chamber, the top plate and the chamber walls forming the reactor anode. The grounded plate is spaced apart from the chamber top plate a distance sufficient to allow a plasma to be established between the grounded plate and the top plate, and the distance between the grounded plate and the cathode is large enough not to disturb the field in the proximity of the wafers being etched. The plate can be apertured to facilitate etchant gas flow. According to another embodiment of the invention at least two grounded plates are employed, spaced apart from each other and from the upper surface of the reactor plasma chamber.

Abstract: A reactive ion etching chamber structure is designed to provide operation with uniformity in electric field and generated plasma so as to produce uniform, contaminant-free etching over large batches of silicon wafers. The anode chamber structure is cylindrical and physically symmetrical with respect to a round cathode plate with the internal surfaces of the chamber being free of any apertures, holes, recesses, or the like, having an opening dimension larger than one tenth the thickness of plasma "dark space". Under normal reactive ion etching conditions, such opening dimension is 1.5 mm or less and the distance between cathode and anode internal surface is 3.0 mm, or less.

Abstract: As etching progresses from one layer of material to another in reactive ion etching systems, the partial pressures of the reaction chamber gas components change. In constant pressure reactive ion etching systems, changes in chamber pressure are corrected by changes in the etchant species flow rate into the reaction chamber. By monitoring flow rate, information is obtained which may be used to identify the points where partial pressures change, and latter may, in turn, be used to derive etching points in the material being etched.