Patents by Inventor Brian Halvorson

Brian Halvorson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10928423
    Abstract: The test system provides an array of test probes. The probes pass through a first or upper probe guide retainer which has a plurality of slot sized to receive the probes in a way that they cannot rotate. A plurality of flex circuits at the different heights engage bottom probe ends at their respective height levels and flex circuits continue the electrical connection from the probes to a load board. The test probes are bonded to the flex circuits by ring shaped flowable conductive material. The flex circuits are biased against a load board by an elastomeric pad of spaced part conical projections.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: February 23, 2021
    Assignee: Johnstech International Corporation
    Inventors: John DeBauche, Dan Campion, Michael Andres, Steve Rott, Jeffrey Sherry, Brian Halvorson, Brian Eshult
  • Patent number: 10330702
    Abstract: A testing device for wafer level testing of IC circuits is disclosed. An upper and lower pin (22, 62) are configured to slide relatively to each other and are held in electrically biased contact by an elastomer (80). To prevent rotation of the pins in the pin guide, a walled recess in the bottom of the pin guide engages flanges on the pins. In another embodiment, the pin guide maintains rotational alignment by being fitted around the pin profile or having projections abutting the pin. The pin guide (12) is maintained in alignment with the retainer 14 by establishing a registration corner (506) and driving the guide into the corner by elastomers in at least one diagonally opposite corner.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: June 25, 2019
    Assignee: Johnstech International Corporation
    Inventors: Jathan Edwards, Charles Marks, Brian Halvorson
  • Publication number: 20190041429
    Abstract: A testing device for wafer level testing of IC circuits is disclosed. An upper and lower pin (22, 62) are configured to slide relatively to each other and are held in electrically biased contact by an elastomer (80). To prevent rotation of the pins in the pin guide, a walled recess in the bottom of the pin guide engages flanges on the pins. In another embodiment, the pin guide maintains rotational alignment by being fitted around the pin profile or having projections abutting the pin. The pin guide (12) is maintained in alignment with the retainer 14 by establishing a registration corner (506) and driving the guide into the corner by elastomers in at least one diagonally opposite corner.
    Type: Application
    Filed: September 18, 2018
    Publication date: February 7, 2019
    Inventors: Jathan Edwards, Charles Marks, Brian Halvorson
  • Publication number: 20190004093
    Abstract: The test system provides an array of test probes. The probes pass through a first or upper probe guide retainer which has a plurality of slot sized to receive the probes in a way that they cannot rotate. A plurality of flex circuits at the different heights engage bottom probe ends at their respective height levels and flex circuits continue the electrical connection from the probes to a load board. The test probes are bonded to the flex circuits by ring shaped flowable conductive material. The flex circuits are biased against a load board by an elastomeric pad of spaced part conical projections.
    Type: Application
    Filed: September 4, 2018
    Publication date: January 3, 2019
    Inventors: John DeBauche, Dan Campion, Michael Andres, Steve Rott, Jeffrey Sherry, Brian Halvorson, Brian Eshult
  • Patent number: 10078101
    Abstract: A testing device for wafer level testing of IC circuits is disclosed. An upper and lower pin (22, 62) are configured to slide relatively to each other and are held in electrically biased contact by an elastomer (80). To prevent rotation of the pins in the pin guide, a walled recess in the bottom of the pin guide engages flanges on the pins. In another embodiment, the pin guide maintains rotational alignment by being fitted around the pin profile or having projections abutting the pin. The pin guide (12) is maintained in alignment with the retainer 14 by establishing a registration corner (506) and driving the guide into the corner by elastomers in at least one diagonally opposite corner.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: September 18, 2018
    Assignee: Johnstech International Corporation
    Inventors: Jathan Edwards, Charles Marks, Brian Halvorson
  • Patent number: 10067164
    Abstract: The test system provides an array of test probes. The probes pass through a first or upper probe guide retainer which has a plurality of slot sized to receive the probes in a way that they cannot rotate. A plurality of flex circuits at the different heights engage bottom probe ends at their respective height levels and flex circuits continue the electrical connection from the probes to a load board. The test probes are bonded to the flex circuits by ring shaped flowable conductive material. The flex circuits are biased against a load board by an elastomeric pad of spaced part conical projections.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: September 4, 2018
    Assignee: Johnstech International Corporation
    Inventors: John DeBauche, Dan Campion, Michael Andres, Steve Rott, Jeffrey Sherry, Brian Halvorson, Brian Eshult
  • Patent number: 9817026
    Abstract: A testing device for wafer level testing of IC circuits is disclosed. An upper and lower pin (22, 62) are configured to slide relatively to each other and are held in electrically biased contact by an elastomer (80). The elastomer is precompressed from its natural rest state between a top (22) plate and a bottom (70). Pre compression improves the resilient response of the pins. The pin crowns (40) are maintained relatively coplanar by the engagement of at least one flange (44a-b) against an up-stop surface 90 of plate 20, thereby insuring coplanarity of the crowns. The pin guide (12) is maintained in alignment with the retainer 14 by establishing a registration corner (506) and driving the guide into the corner by elastomers in at least one diagonally opposite corner.
    Type: Grant
    Filed: February 15, 2016
    Date of Patent: November 14, 2017
    Assignee: Johnstech International Corporation
    Inventors: Jathan Edwards, Charles Marks, Brian Halvorson
  • Patent number: 9696347
    Abstract: The test system provides an array of test probes having a cross beam. The probes pass through a first or upper probe guide retainer which has a plurality of slot sized to receive the probes in a way that they cannot rotate. The probes are biased upwardly through the retainer by an elastomeric block having a similar array of slots. The elastomer is then capped at its bottom by a second or lower retainer with like slots to form a sandwich with the elastomer therebetween. The bottom ends of the probes are group by probe height. A plurality of flex circuits at the different heights engage bottom probe ends at their respective height levels and take continue the circuits to a probe card where test signals originate.
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: July 4, 2017
    Assignee: Johnstech International Corporation
    Inventors: John DeBauche, Dan Campion, Michael Andres, Steve Rott, Jeffrey Sherry, Brian Halvorson, Brian Eshult
  • Publication number: 20170074926
    Abstract: A testing device for wafer level testing of IC circuits is disclosed. An upper and lower pin (22, 62) are configured to slide relatively to each other and are held in electrically biased contact by an elastomer (80). To prevent rotation of the pins in the pin guide, a walled recess in the bottom of the pin guide engages flanges on the pins. In another embodiment, the pin guide maintains rotational alignment by being fitted around the pin profile or having projections abutting the pin. The pin guide (12) is maintained in alignment with the retainer 14 by establishing a registration corner (506) and driving the guide into the corner by elastomers in at least one diagonally opposite corner.
    Type: Application
    Filed: March 10, 2015
    Publication date: March 16, 2017
    Inventors: Jathan Edwards, Charles Marks, Brian Halvorson
  • Publication number: 20170059616
    Abstract: The test system provides an array of test probes. The probes pass through a first or upper probe guide retainer which has a plurality of slot sized to receive the probes in a way that they cannot rotate. A plurality of flex circuits at the different heights engage bottom probe ends at their respective height levels and flex circuits continue the electrical connection from the probes to a load board. The test probes are bonded to the flex circuits by ring shaped flowable conductive material. The flex circuits are biased against a load board by an elastomeric pad of spaced part conical projections.
    Type: Application
    Filed: August 24, 2016
    Publication date: March 2, 2017
    Inventors: John DeBauche, Dan Campion, Michael Andres, Steve Rott, Jeffrey Sherry, Brian Halvorson, Brian Eshult
  • Publication number: 20160161528
    Abstract: A testing device for wafer level testing of IC circuits is disclosed. An upper and lower pin (22, 62) are configured to slide relatively to each other and are held in electrically biased contact by an elastomer (80). The elastomer is precompressed from its natural rest state between a top (22) plate and a bottom (70). Pre compression improves the resilient response of the pins. The pin crowns (40) are maintained relatively coplanar by the engagement of at least one flange (44a-b) against an up-stop surface 90 of plate 20, thereby insuring coplanarity of the crowns. The pin guide (12) is maintained in alignment with the retainer 14 by establishing a registration corner (506) and driving the guide into the corner by elastomers in at least one diagonally opposite corner.
    Type: Application
    Filed: February 15, 2016
    Publication date: June 9, 2016
    Inventors: Jathan Edwards, Charles Marks, Brian Halvorson
  • Patent number: 9261537
    Abstract: A testing device for wafer level testing of IC circuits is disclosed. An upper and lower pin (22, 62) are configured to slide relatively to each other and are held in electrically biased contact by an elastomer (80). The elastomer is precompressed from its natural rest state between a top (22) plate and a bottom (70). Pre compression improves the resilient response of the pins. The pin crows (40) are maintained relatively coplanar by the engagement of at least one flang (44a-b) against an up-stop surface 90 of plate 20, thereby insuring coplanarity of the crowns. The pin guide (12) is maintained in alignment with the retainer 14 by establishing a registration corner (506) and driving the guide into the corner by elastomers in at least one diagonally opposite corner.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: February 16, 2016
    Assignee: Johnstech International Corporation
    Inventors: Jathan Edwards, Charles Marks, Brian Halvorson
  • Publication number: 20150015287
    Abstract: The test system provides an array of test probes having a cross beam. The probes pass through a first or upper probe guide retainer which has a plurality of slot sized to receive the probes in a way that they cannot rotate. The probes are biased upwardly through the retainer by an elastomeric block having a similar array of slots. The elastomer is then capped at its bottom by a second or lower retainer with like slots to form a sandwich with the elastomer therebetween. The bottom ends of the probes are group by probe height. A plurality of flex circuits at the different heights engage bottom probe ends at their respective height levels and take continue the circuits to a probe card where test signals originate.
    Type: Application
    Filed: July 10, 2014
    Publication date: January 15, 2015
    Inventors: John DeBauche, Dan Campion, Michael Andres, Steve Rott, Jeffrey Sherry, Brian Halvorson, Brian Eshult
  • Publication number: 20130342233
    Abstract: A testing device for wafer level testing of IC circuits is disclosed. An upper and lower pin (22, 62) are configured to slide relatively to each other and are held in electrically biased contact by an elastomer (80). The elastomer is precompressed from its natural rest state between a top (22) plate and a bottom (70). Pre compression improves the resilient response of the pins. The pin crows (40) are maintained relatively coplanar by the engagement of at least one flang (44a-b) against an up-stop surface 90 of plate 20, thereby insuring coplanarity of the crowns. The pin guide (12) is maintained in alignment with the retainer 14 by establishing a registration corner (506) and driving the guide into the corner by elastomers in at least one diagonally opposite corner.
    Type: Application
    Filed: June 19, 2013
    Publication date: December 26, 2013
    Inventors: Jathan Edwards, Charles Marks, Brian Halvorson