Abstract: A method of fabricating a Metal-Oxide Semiconductor (MOS) transistor includes providing a substrate having a substrate surface doped with a second dopant type and a gate stack over the substrate surface, and a masking pattern on the substrate surface which exposes a portion of the substrate surface for ion implantation. A first pocket implantation uses the second dopant type with the masking pattern on the substrate surface. At least one retrograde gate edge diode leakage (GDL) reduction pocket implantation uses the first dopant type with the masking pattern on the substrate surface. The first pocket implant and retrograde GDL reduction pocket implant are annealed. After annealing, the first pocket implant provides first pocket regions and the retrograde GDL reduction pocket implant provides an overlap with the first pocket regions to form a first counterdoped pocket portion within the first pocket regions.

Abstract: A method of fabricating a Metal-Oxide Semiconductor (MOS) transistor includes providing a substrate having a substrate surface doped with a second dopant type and a gate stack over the substrate surface, and a masking pattern on the substrate surface which exposes a portion of the substrate surface for ion implantation. A first pocket implantation uses the second dopant type with the masking pattern on the substrate surface. At least one retrograde gate edge diode leakage (GDL) reduction pocket implantation uses the first dopant type with the masking pattern on the substrate surface. The first pocket implant and retrograde GDL reduction pocket implant are annealed. After annealing, the first pocket implant provides first pocket regions and the retrograde GDL reduction pocket implant provides an overlap with the first pocket regions to form a first counterdoped pocket portion within the first pocket regions.

Abstract: A semiconductor device and a method for fabricating a semiconductor device with reduced line bending is provided. The method can include forming a first layer and depositing a photoresist layer on the first layer. The photoresist layer can be patterned, such that the patterning comprises at least one support feature disposed adjacent to an outside of a corner feature.

Abstract: The present invention provides, in one embodiment, a method of fabricating a semiconductor device (100). In one embodiment, the method includes growing an oxide layer 120 from a substrate 104, 106 over a first dopant region 122 and a second dopant region 128, implanting a first dopant through the oxide layer 120, into the substrate 104 in the first dopant region 122, and adjacent a gate structure 114, and substantially removing the oxide layer 120 from the substrate within the second dopant region 128. Subsequent to the removal of the oxide layer 120 in the second dopant region 128, a second dopant that is opposite in type to the first dopant is implanted into the substrate 106 and within the second dopant region 128 and adjacent a gate structure 114.

Abstract: The present invention teaches the formation of CMOS transistors using interfacial nitrogen at the interface between the lightly doped extension regions and an overlying insulating layer in combination with a capping layer of silicon nitride, both prior to the final source/drain anneal. Doses and energies may be increased for the P-channel lightly-doped drain, source and drain regions. The resulting transistors exhibit desirably high drive current and low off-state leakage current and overlap capacitance.

Abstract: The present invention provides, in one embodiment, a method of fabricating a semiconductor device (100). The method comprises growing an oxide layer (120) on a gate structure (114) and a substrate (102) and implanting a dopant (124) into the substrate (102) and the oxide layer (120). Implantation is such that a portion of the dopant (124) remains in the oxide layer (120) to form an implanted oxide layer (126). The method further includes depositing a protective oxide layer (132) on the implanted oxide layer (126) and forming etch-resistant off-set spacers (134). The etch-resistant off-set spacers (134) are formed adjacent sidewalls of the gate structure (114) and on the protective oxide layer (132). The etch resistant off-set spacers having an inner perimeter (135) adjacent the sidewalls and an opposing outer perimeter (136). The method also comprises removing portions of the protective oxide layer (132) lying outside the outer perimeter (136) of the etch-resistant off-set spacers (134).

Abstract: The present invention provides, in one embodiment, a method of fabricating a semiconductor device (100). The method comprises growing an oxide layer (120) on a gate structure (114) and a substrate (102) and implanting a dopant (124) into the substrate (102) and the oxide layer (120). Implantation is such that a portion of the dopant (124) remains in the oxide layer (120) to form an implanted oxide layer (126). The method further includes depositing a protective oxide layer (132) on the implanted oxide layer (126) and forming etch-resistant off-set spacers (134). The etch-resistant off-set spacers (134) are formed adjacent sidewalls of the gate structure (114) and on the protective oxide layer (132). The etch resistant off-set spacers having an inner perimeter (135) adjacent the sidewalls and an opposing outer perimeter (136). The method also comprises removing portions of the protective oxide layer (132) lying outside the outer perimeter (136) of the etch-resistant off-set spacers (134).

Abstract: The present invention teaches the formation of CMOS transistors using interfacial nitrogen at the interface between the lightly doped extension regions and an overlying insulating layer in combination with a capping layer of silicon nitride, both prior to the final source/drain anneal. Doses and energies may be increased for the P-channel lightly-doped drain, source and drain regions. The resulting transistors exhibit desirably high drive current and low off-state leakage current and overlap capacitance.