Patents by Inventor Brian J. Griffiths
Brian J. Griffiths has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11992165Abstract: Self-cleaning features for extraction cleaners and attachments for extraction cleaners, such as accessory tools, wands, and/or hoses, are provided. The self-cleaning features are configured redirect cleaning fluid from a fluid supply system of the extraction cleaner into a working air or fluid recovery path of the extraction cleaner, including, but not limited to into the working air or fluid recovery path of a tool, wand, and/or hose of the extraction cleaner.Type: GrantFiled: April 17, 2023Date of Patent: May 28, 2024Assignee: BISSELL Inc.Inventors: Victoria J. Royale, Aaron P. Griffith, David M. Miller, Michael Luyckx, Brian C. Wolfe, Justin Benacquisto
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Patent number: 11194978Abstract: An apparatus and method for combined radio frequency identification (RFID)-based asset management and component authentication are provided. The apparatus comprises a plurality of components to be authenticated, a memory configured to store inventory data, a plurality of root-of-trust (RoT) integrated circuits (ICs), a wired communication bus, and a radio frequency identification (RFID) relay tag. Each RoT IC is mechanically coupled to a corresponding one of the plurality of components and configured to generate authentication data based on a unique key generated for authenticating the corresponding component. The RFID relay tag is connected to each of the RoT ICs via the wired communication bus and is configured to communicate with each of the RoT ICs via the wired communication bus and pass the authentication data and the inventory data to an RFID reader via a radio frequency signal to facilitate authentication of components and inventory management.Type: GrantFiled: July 12, 2019Date of Patent: December 7, 2021Assignees: Northrop Grumman Systems Corporation, RFID Global Solution, Inc.Inventors: Scott K. Suko, Diana S. Hage, Brian J. Griffiths, Parrish E. Ralston
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Patent number: 10963031Abstract: A server system includes a common power bus, a power supply to provide direct current (DC) power through the common power bus, at least one node including a processor to receive the DC power through the common power bus, a transmitter capacitive coupled to the common power bus to transmit a power information signal from the power supply through the common power bus, and at least one receiver capacitive coupled to the common power bus to receive the power information signal transmitted by the transmitter and to provide the received power information signal to the at least one node. A plurality of buffers respectively coupled between the common power bus and each of the power supply and the at least one node provide path separation for high frequency and low frequency currents.Type: GrantFiled: February 27, 2018Date of Patent: March 30, 2021Assignee: Intel CorporationInventors: Brian J. Griffith, Viktor D. Vogman, Justin J. Song
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Publication number: 20210012073Abstract: An apparatus and method for combined radio frequency identification (RFID)-based asset management and component authentication are provided. The apparatus comprises a plurality of components to be authenticated, a memory configured to store inventory data, a plurality of root-of-trust (RoT) integrated circuits (ICs), a wired communication bus, and a radio frequency identification (RFID) relay tag. Each RoT IC is mechanically coupled to a corresponding one of the plurality of components and configured to generate authentication data based on a unique key generated for authenticating the corresponding component. The RFID relay tag is connected to each of the RoT ICs via the wired communication bus and is configured to communicate with each of the RoT ICs via the wired communication bus and pass the authentication data and the inventory data to an RFID reader via a radio frequency signal to facilitate authentication of components and inventory management.Type: ApplicationFiled: July 12, 2019Publication date: January 14, 2021Inventors: Scott K. Suko, Diana S. Hage, Brian J. Griffiths, Parrish E. Ralston
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Patent number: 10719107Abstract: A method and apparatus for node power regulation among nodes that share a power supply are described. In one embodiment, the apparatus comprises a power supply unit to provide input power and a plurality of nodes coupled to receive the input power, where each node of the plurality of nodes is operable to run power management logic, and wherein two or more nodes of the plurality of nodes alternate between performing power management and providing power regulation control information to other nodes of the plurality of nodes to regulate power consumption by the plurality of nodes, with, at any one time, only one node of plurality of nodes generating the power regulation control to regulate power for the plurality of nodes.Type: GrantFiled: March 29, 2016Date of Patent: July 21, 2020Assignee: INTEL CORPORATIONInventors: Justin J. Song, Devadatta V. Bodas, Muralidhar Rajappa, Brian J. Griffith, Andy Hoffman, Gopal R. Mundada
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Patent number: 10564709Abstract: Voltage regulation techniques for electronic devices are described. In one embodiment, for example, an apparatus may comprise an electronic element comprising one or more integrated circuits, a voltage regulator to regulate an input voltage of the electronic element, the voltage regulator to source an output current comprising at least a portion of an input current of the electronic element, the voltage regulator to operate in a current-limiting mode to limit the output current when the input current exceeds a threshold current, and a capacitor bank comprising one or more capacitors, the capacitor bank to source a supplemental current to supplement the output current of the voltage regulator when the voltage regulator operates in the current-limiting mode. Other embodiments are described and claimed.Type: GrantFiled: July 30, 2018Date of Patent: February 18, 2020Assignee: INTEL CORPORATIONInventors: Brian J. Griffith, Viktor D. Vogman
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Patent number: 10429912Abstract: A processor is described that includes a quick signal path from an input of the processor to logic circuitry within the processor. The input is to receive a fast throttle down signal. The logic circuitry is to throttle down a rate at which the processor issues instructions for execution in response to the fast throttle down signal. The quick signal path is to impose practicably minimal propagation delay of the fast throttle down signal within the processor.Type: GrantFiled: December 18, 2017Date of Patent: October 1, 2019Assignee: Intel CorporationInventors: Krishnakanth Sistla, Martin Rowland, Efraim Rotem, Brian J. Griffith, Ankush Varma, Anupama Suryanarayanan
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Publication number: 20190064917Abstract: Voltage regulation techniques for electronic devices are described. In one embodiment, for example, an apparatus may comprise an electronic element comprising one or more integrated circuits, a voltage regulator to regulate an input voltage of the electronic element, the voltage regulator to source an output current comprising at least a portion of an input current of the electronic element, the voltage regulator to operate in a current-limiting mode to limit the output current when the input current exceeds a threshold current, and a capacitor bank comprising one or more capacitors, the capacitor bank to source a supplemental current to supplement the output current of the voltage regulator when the voltage regulator operates in the current-limiting mode. Other embodiments are described and claimed.Type: ApplicationFiled: July 30, 2018Publication date: February 28, 2019Applicant: INTEL CORPORATIONInventors: BRIAN J. GRIFFITH, VIKTOR D. VOGMAN
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Publication number: 20190053397Abstract: The present disclosure describes a number of embodiments related to devices, systems, and methods for identifying a location of a resource among a plurality of locations in a data center rack. A signal transmission medium may be disposed proximate to the plurality of locations to transmit a signal traversing the plurality of locations, with each resource in the rack having a sensor or transmitter portion that couples itself to the signal transmission medium at a point substantially at this resource location, or the location of the resource within the data center rack is identified based at least in part on the sensed signal.Type: ApplicationFiled: January 12, 2018Publication date: February 14, 2019Inventors: Thane M. Larson, Vasudevan Srinivasan, Murugasmy K. Nachimuthu, Brian J. Griffith
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Publication number: 20180232024Abstract: A processor is described that includes a quick signal path from an input of the processor to logic circuitry within the processor. The input is to receive a fast throttle down signal. The logic circuitry is to throttle down a rate at which the processor issues instructions for execution in response to the fast throttle down signal. The quick signal path is to impose practicably minimal propagation delay of the fast throttle down signal within the processor.Type: ApplicationFiled: December 18, 2017Publication date: August 16, 2018Inventors: Krishnakanth Sistla, Martin Rowland, Efraim Rotem, Brian J. Griffith, Ankush Varma, Anupama Suryanarayanan
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Patent number: 10037075Abstract: Voltage regulation techniques for electronic devices are described. In one embodiment, for example, an apparatus may comprise an electronic element comprising one or more integrated circuits, a voltage regulator to regulate an input voltage of the electronic element, the voltage regulator to source an output current comprising at least a portion of an input current of the electronic element, the voltage regulator to operate in a current-limiting mode to limit the output current when the input current exceeds a threshold current, and a capacitor bank comprising one or more capacitors, the capacitor bank to source a supplemental current to supplement the output current of the voltage regulator when the voltage regulator operates in the current-limiting mode. Other embodiments are described and claimed.Type: GrantFiled: April 2, 2016Date of Patent: July 31, 2018Assignee: INTEL CORPORATIONInventors: Brian J. Griffith, Viktor D. Vogman
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Publication number: 20180188790Abstract: A server system includes a common power bus, a power supply to provide direct current (DC) power through the common power bus, at least one node including a processor to receive the DC power through the common power bus, a transmitter capacitive coupled to the common power bus to transmit a power information signal from the power supply through the common power bus, and at least one receiver capacitive coupled to the common power bus to receive the power information signal transmitted by the transmitter and to provide the received power information signal to the at least one node. A plurality of buffers respectively coupled between the common power bus and each of the power supply and the at least one node provide path separation for high frequency and low frequency currents.Type: ApplicationFiled: February 27, 2018Publication date: July 5, 2018Applicant: INTEL CORPORATIONInventors: Brian J. Griffith, Viktor D. Vogman, Justin J. Song
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Patent number: 9971391Abstract: A method of assessing energy efficiency of a High-performance computing (HPC) system, including: selecting a plurality of HPC workloads to run on a system under test (SUT) with one or more power constraints, wherein the SUT includes a plurality of HPC nodes in the HPC system, executing the plurality of HPC workloads on the SUT, and generating a benchmark metric for the SUT based on a baseline configuration for each selected HPC workload and a plurality of measured performance per power values for each executed workload at each selected power constraint is shown.Type: GrantFiled: December 23, 2015Date of Patent: May 15, 2018Assignee: Intel CorporationInventors: Devadatta Bodas, Meenakshi Arunachalam, Ilya Sharapov, Charles R. Yount, Scott B. Huck, Ramakrishna Huggahalli, Justin J. Song, Brian J. Griffith, Muralidhar Rajappa, Lingdan (Linda) Zeng
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Patent number: 9933829Abstract: A server system includes a common power bus, a power supply to provide direct current (DC) power through the common power bus, at least one node including a processor to receive the DC power through the common power bus, a transmitter capacitive coupled to the common power bus to transmit a power information signal from the power supply through the common power bus, and at least one receiver capacitive coupled to the common power bus to receive the power information signal transmitted by the transmitter and to provide the received power information signal to the at least one node. A plurality of buffers respectively coupled between the common power bus and each of the power supply and the at least one node provide path separation for high frequency and low frequency currents.Type: GrantFiled: September 7, 2016Date of Patent: April 3, 2018Assignee: INTEL CORPORATIONInventors: Brian J. Griffith, Viktor D. Vogman, Justin J. Song
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Patent number: 9846463Abstract: A processor is described that includes a quick signal path from an input of the processor to logic circuitry within the processor. The input is to receive a fast throttle down signal. The logic circuitry is to throttle down a rate at which the processor issues instructions for execution in response to the fast throttle down signal. The quick signal path is to impose practicably minimal propagation delay of the fast throttle down signal within the processor.Type: GrantFiled: September 28, 2012Date of Patent: December 19, 2017Assignee: Intel CorporationInventors: Krishnakanth Sistla, Martin Mark Rowland, Efraim Rotem, Brian J. Griffith, Ankush Varma, Anupama Suryanarayanan
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Publication number: 20170285702Abstract: A method and apparatus for node power regulation among nodes that share a power supply are described. In one embodiment, the apparatus comprises a power supply unit to provide input power and a plurality of nodes coupled to receive the input power, where each node of the plurality of nodes is operable to run power management logic, and wherein two or more nodes of the plurality of nodes alternate between performing power management and providing power regulation control information to other nodes of the plurality of nodes to regulate power consumption by the plurality of nodes, with, at any one time, only one node of plurality of nodes generating the power regulation control to regulate power for the plurality of nodes.Type: ApplicationFiled: March 29, 2016Publication date: October 5, 2017Inventors: Justin J. Song, Devadatta V. Bodas, Muralidhar Rajappa, Brian J. Griffith, Andy Hoffman, Gopal R. Mundada
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Publication number: 20170285711Abstract: Voltage regulation techniques for electronic devices are described. In one embodiment, for example, an apparatus may comprise an electronic element comprising one or more integrated circuits, a voltage regulator to regulate an input voltage of the electronic element, the voltage regulator to source an output current comprising at least a portion of an input current of the electronic element, the voltage regulator to operate in a current-limiting mode to limit the output current when the input current exceeds a threshold current, and a capacitor bank comprising one or more capacitors, the capacitor bank to source a supplemental current to supplement the output current of the voltage regulator when the voltage regulator operates in the current-limiting mode. Other embodiments are described and claimed.Type: ApplicationFiled: April 2, 2016Publication date: October 5, 2017Applicant: INTEL CORPORATIONInventors: BRIAN J. GRIFFITH, VIKTOR D. VOGMAN
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Publication number: 20170185132Abstract: A method of assessing energy efficiency of a High-performance computing (HPC) system, including: selecting a plurality of HPC workloads to run on a system under test (SUT) with one or more power constraints, wherein the SUT includes a plurality of HPC nodes in the HPC system, executing the plurality of HPC workloads on the SUT, and generating a benchmark metric for the SUT based on a baseline configuration for each selected HPC workload and a plurality of measured performance per power values for each executed workload at each selected power constraint is shown.Type: ApplicationFiled: December 23, 2015Publication date: June 29, 2017Inventors: Devadatta Bodas, Meenakshi Arunachalam, Ilya Sharapov, Charles R. Yount, Scott B. Huck, Ramakrishna Huggahalli, Justin J. Song, Brian J. Griffith, Muralidhar Rajappa, Lingdan (Linda) Zeng
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Publication number: 20160380675Abstract: A server system includes a common power bus, a power supply to provide direct current (DC) power through the common power bus, at least one node including a processor to receive the DC power through the common power bus, a transmitter capacitive coupled to the common power bus to transmit a power information signal from the power supply through the common power bus, and at least one receiver capacitive coupled to the common power bus to receive the power information signal transmitted by the transmitter and to provide the received power information signal to the at least one node. A plurality of buffers respectively coupled between the common power bus and each of the power supply and the at least one node provide path separation for high frequency and low frequency currents.Type: ApplicationFiled: September 7, 2016Publication date: December 29, 2016Applicant: INTEL CORPORATIONInventors: Brian J. Griffith, Viktor D. Vogman, Justin J. Song
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Patent number: 9461709Abstract: A server system includes a common power bus, a power supply to provide direct current (DC) power through the common power bus, at least one node including a processor to receive the DC power through the common power bus, a transmitter capacitive coupled to the common power bus to transmit a power information signal from the power supply through the common power bus, and at least one receiver capacitive coupled to the common power bus to receive the power information signal transmitted by the transmitter and to provide the received power information signal to the at least one node. A plurality of buffers respectively coupled between the common power bus and each of the power supply and the at least one node provide path separation for high frequency and low frequency currents.Type: GrantFiled: June 30, 2014Date of Patent: October 4, 2016Assignee: INTEL CORPORATIONInventors: Brian J. Griffith, Viktor D. Vogman, Justin J. Song