Abstract: An apparatus for use in a solar energy facility including a plurality of photovoltaic systems distributed over a local area and a plurality of tracking systems that operate to control orientation of corresponding photovoltaic systems. Each tracking system includes a tracking control unit that employs a wireless network interface for wireless communication over the local area. The apparatus includes a wireless network interface for wireless communication over the local area, a plurality of sensors including a GPS receiver module and an anemometer, a microcontroller operably coupled to the wireless network interface and to the plurality of sensors, a power supply unit (including means for storage of electrical energy) for supplying DC power signals to the apparatus, and at least one photovoltaic cell for converting solar insolation into DC power supply signals that are supplied to the electrical energy storage means of the power supply unit.

Abstract: A memory device, based upon a field effect transistor having a floating gate is constructed for use in a silicon integrated circuit array of similar memory devices. The memory device includes only two polysilicon layers, a portion of each polysilicon layer being connected to each other through a via hole in an intervening silicon dioxide layer to form the floating gate.

Abstract: A memory device, based upon a field effect transistor having a floating gate is constructed for use in a silicon integrated circuit array of similar memory devices. The memory device includes only two polysilicon layers, a portion of each polysilicon layer being connected to each other through a via hole in an intervening silicon dioxide layer to form the floating gate.

Abstract: A method of forming an aligned vertical oxide fuse and emitter using a single mask. The mask includes an opening through which impurities are introduced into the base region through a first layer of insulation and which is subsequently used to form the emitter aperture through the first insulative layer. The thin fuse oxide is formed by non-selective oxidation after removal of the mask. Alternatively, the impurities may also be introduced through the emitter aperture or from doped thin fuse oxide after removal of the mask. The resulting integrated circuit includes at least three regions of oxidation of three thicknesses, in descending order, field oxide, device opening or gate oxide and fuse oxide.

Abstract: A supply voltage switch circuit for use with programable arrays such as EPROMS includes a pair of P-channel transistor switches connected in series between a high programing supply voltage and a low read supply voltage wherein the circuit junction between the transistors is connected to a row/column-select supply line. A switch control circuit is connected to the switches to alternately connect the row/column-select supply line to one or the other of the supply voltages in response to a logic signal. A third P-channel transistor may be connected in the series circuit, under control of the logic signal, to prevent destructive transient currents from flowing when powering up the high supply voltage source, at which occasions both of the two principal switches tend to momentarily turn on.

Abstract: A method of forming an aligned vertical oxide fuse and emitter using a single mask. The mask includes an opening through which impurities are introduced into the base region through a first layer of insulation and which is subsequently used to form the emitter aperture through the first insulative layer. The thin fuse oxide is formed by non-selective oxidation after removal of the mask. Alternatively, the impurities may also be introduced through the emitter aperture or from doped thin fuse oxide after removal of the mask. The resulting integrated circuit includes at least three regions of oxidation of three thicknesses, in descending order, field oxide, device opening or gate oxide and fuse oxide.

Abstract: A circuitry and method of testing programmable, variable threshold memory cells by applying a variable voltage above a normal read voltage to the control gate of a high threshold cell to determine the actual high threshold value and applying zero voltage to the control gate of a low threshold cell to determine if the low threshold is of the opposite polarity of the high threshold.