Patents by Inventor Brian King Flachs
Brian King Flachs has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10345882Abstract: A dynamic power meter circuit receives a set of clock signals. The clock signals are summed by a clock sum adder, thereby generating a clock sum value. A dynamic power meter output value is generated based at least in part on the clock sum value. In one particular example, a dynamic power meter circuit receives clock signals and from them generates a clock sum model sub-value. The dynamic power meter circuit also receives event signals, and from them generates an architectural event model sub-value. A corresponding pair of clock sum model sub-value and architectural event model sub-value are then ratiometrically combined, thereby generating a dynamic power meter output value. Due to the use of both event signals and clock signals, a stream of dynamic power meter output values is generated that more closely tracks actual dynamic power of a circuit being monitored.Type: GrantFiled: November 5, 2015Date of Patent: July 9, 2019Assignee: MEDIATEK INC.Inventors: Huajun Wen, Hugh Thomas Mair, Hsin-Chen Chen, Brian King Flachs
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Publication number: 20160291068Abstract: A dynamic power meter circuit receives a set of clock signals. The clock signals are summed by a clock sum adder, thereby generating a clock sum value. A dynamic power meter output value is generated based at least in part on the clock sum value. In one particular example, a dynamic power meter circuit receives clock signals and from them generates a clock sum model sub-value. The dynamic power meter circuit also receives event signals, and from them generates an architectural event model sub-value. A corresponding pair of clock sum model sub-value and architectural event model sub-value are then ratiometrically combined, thereby generating a dynamic power meter output value. Due to the use of both event signals and clock signals, a stream of dynamic power meter output values is generated that more closely tracks actual dynamic power of a circuit being monitored.Type: ApplicationFiled: November 5, 2015Publication date: October 6, 2016Inventors: Huajun Wen, Hugh Thomas Mair, Hsin-Chen Chen, Brian King Flachs
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Patent number: 8145804Abstract: A bi-endian multiprocessor system having multiple processing elements, each of which includes a processor core, a local memory and a memory flow controller. The memory flow controller transfers data between the local memory and data sources external to the processing element. If the processing element and the data source implement data representations having the same endian-ness, each multi-word line of data is stored in the local memory in the same word order as in the data source. If the processing element and the data source implement data representations having different endian-ness, the words of each multi-word line of data are transposed when data is transferred between local memory and the data source. The processing element may incorporate circuitry to add doublewords, wherein the circuitry can alternately carry bits from a first word to a second word or vice versa, depending upon whether the words in lines of data are transposed.Type: GrantFiled: September 21, 2009Date of Patent: March 27, 2012Assignees: Kabushiki Kaisha Toshiba, International Business Machines CorporationInventors: Brian King Flachs, Brad William Michael, Nicolas Maeding, Shigeaki Iwasa, Seiji Maeda, Hiroo Hayashi
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Publication number: 20110072170Abstract: A bi-endian multiprocessor system having multiple processing elements, each of which includes a processor core, a local memory and a memory flow controller. The memory flow controller transfers data between the local memory and data sources external to the processing element. If the processing element and the data source implement data representations having the same endian-ness, each multi-word line of data is stored in the local memory in the same word order as in the data source. If the processing element and the data source implement data representations having different endian-ness, the words of each multi-word line of data are transposed when data is transferred between local memory and the data source. The processing element may incorporate circuitry to add doublewords, wherein the circuitry can alternately carry bits from a first word to a second word or vice versa, depending upon whether the words in lines of data are transposed.Type: ApplicationFiled: September 21, 2009Publication date: March 24, 2011Inventors: Brian King Flachs, Brad William Michael, Nicolas Maeding, Shigeaki Iwasa, Seiji Maeda, Hiroo Hayashi
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Patent number: 7836222Abstract: An apparatus which uses channel counters in combination with channel count read instructions as a means of providing information that data in a given channel is valid or has not been previously read. The counter may also, in the situation of the channel being defined as blocking, be used to prevent the unintentional overwriting of data in a register used by the channel or, alternatively, prevent further communications with the device assigned to that channel when a given count occurs. Intelligent external devices may also use channel count read instructions sent to the counting mechanism for reading from and writing to the channel.Type: GrantFiled: June 26, 2003Date of Patent: November 16, 2010Assignee: International Business Machines CorporationInventors: Michael Norman Day, Brian King Flachs, Harm Peter Hofstee, Charles Ray Johns, John Samuel Liberty
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Patent number: 7617338Abstract: A system for a processor with memory with combined line and word access is presented. A system performs narrow read/write memory accesses and wide read/write memory accesses to the same memory bank using multiplexers and latches to direct data. The system processes 16 byte load/sore requests using a narrow read/write memory access and also processes 128 byte DMA and instruction fetch requests using a wide read/write memory access. During DMA requests, the system writes/reads sixteen DMA operations to memory on one instruction cycle. By doing this, the memory is available to process load/store or instruction fetch requests during fifteen other instruction cycles.Type: GrantFiled: February 3, 2005Date of Patent: November 10, 2009Assignee: International Business Machines CorporationInventors: Sang Hoo Dhong, Brian King Flachs, Harm Peter Hofstee, Osamu Takahashi
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Patent number: 7318182Abstract: The present invention provides for a method for memory array verification. Initialization commands are received and memory array initialization settings are generated based on received initialization commands. The memory array initialization settings are stored in a memory array. A deterministic read output function for the memory array is identified and a logic built-in self test scan on the memory array is performed based on the identified deterministic read output function.Type: GrantFiled: December 2, 2004Date of Patent: January 8, 2008Assignee: International Business Machines CorporationInventors: Louis Bernard Bushard, Sang Hoo Dhong, Brian King Flachs, Osamu Takahashi, Michael Brian White
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Patent number: 7197655Abstract: Disclosed is an apparatus which places computer program instructions into instruction channels in accordance with predefined criteria such that at least some external event instructions are placed in a special “blocking channel.” The number of instructions, in a channel, is monitored in channel specific counters. When a computer processor is awaiting a response from an external entity event (in other words, is blocked from proceeding with the operation the PU is attempting), as signified by the blocking counter being at a predetermined value, the entire PU or at least processor auxiliary components that would be idle, such as math logic, while awaiting an external event response, are deactivated to save power until an awaited external event response is received.Type: GrantFiled: June 26, 2003Date of Patent: March 27, 2007Assignee: International Business Machines CorporationInventors: Brian King Flachs, John Samuel Liberty, Harm Peter Hofstee
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Publication number: 20040268164Abstract: Disclosed is an apparatus which places computer program instructions into instruction channels in accordance with predefined criteria such that at least some external event instructions are placed in a special “blocking channel.” The number of instructions, in a channel, is monitored in channel specific counters. When a computer processor is awaiting a response from an external entity event (in other words, is blocked from proceeding with the operation the PU is attempting), as signified by the blocking counter being at a predetermined value, the entire PU or at least processor auxiliary components that would be idle, such as math logic, while awaiting an external event response, are deactivated to save power until an awaited external event response is received.Type: ApplicationFiled: June 26, 2003Publication date: December 30, 2004Applicant: International Business Machines CorporationInventors: Brian King Flachs, John Samuel Liberty, Harm Peter Hofstee
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Publication number: 20040264445Abstract: An apparatus which uses channel counters in combination with channel count read instructions as a means of providing information that data in a given channel is valid or has not been previously read. The counter may also, in the situation of the channel being defined as blocking, be used to prevent the unintentional overwriting of data in a register used by the channel or, alternatively, prevent further communications with the device assigned to that channel when a given count occurs. Intelligent external devices may also use channel count read instructions sent to the counting mechanism for reading from and writing to the channel.Type: ApplicationFiled: June 26, 2003Publication date: December 30, 2004Applicant: International Business Machines CorporationInventors: Michael Norman Day, Brian King Flachs, Harm Peter Hofstee, Charles Rdy Johns, John Samuel Liberty
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Patent number: 6629235Abstract: A condition code register architecture for supporting multiple execution units is disclosed. A master execution unit is coupled a master condition code register such that condition codes generated by the master execution unit are stored in the master condition code register. A non-master execution unit is coupled to a shadow condition code register such that condition codes generated by the non-master execution unit are stored in the shadow condition code register. A tag unit coupled to the master execution unit and the non-master execution unit such that an entry within the master condition code register can be read only when a corresponding entry within the tag unit is referenced to the master execution unit or the master condition code register.Type: GrantFiled: May 5, 2000Date of Patent: September 30, 2003Assignee: International Business Machines CorporationInventors: Brian King Flachs, Harm Peter Hofstee, Kevin John Nowka
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Patent number: 6600959Abstract: A method and apparatus for using dynamic programmable logic arrays in microprocessor control logic provide decreased power and increased clock frequencies for data processing systems, by using programmable logic arrays exclusively for the control logic. The method and apparatus further simplify the design of the control logic and closure of timing within the microprocessor, by providing overlap of control logic evaluations and data transfers within the microprocessor.Type: GrantFiled: February 4, 2000Date of Patent: July 29, 2003Assignee: International Business Machines CorporationInventors: Paula Kristine Coulman, Sang Hoo Dhong, Brian King Flachs, Harm Peter Hofstee, Jaehong Park, Stephen Douglas Posluszny, Joel Abraham Silberman, Osamu Takahashi
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Patent number: 6598153Abstract: A processor that promotes accelerated resolution of conditional branch instructions includes an instruction sequencer that fetches a plurality of instructions and a detector that detects, among the plurality of fetched instructions, a condition-setting instruction and a conditional branch instruction that depends upon the condition-setting instruction. The processor further includes a decoder that decodes the conditional branch instruction to produce a decoded condition type and an execution unit. In response to the detection of the condition-setting instruction and the conditional branch instruction, the execution unit resolves the conditional branch instruction by evaluating the condition-setting instruction and the decoded condition type in a single operation. Because the condition code bits are not computed or stored as an intermediate result as in prior art processors, branch resolution is accelerated.Type: GrantFiled: December 10, 1999Date of Patent: July 22, 2003Assignee: International Business Machines CorporationInventors: Brian King Flachs, Harm Peter Hofstee, Kevin John Nowka