Abstract: A method for storing a temperature threshold in an integrated circuit includes measuring operating parameters of the integrated circuit versus temperature, calculating a maximum temperature at which the integrated circuit performance exceeds predetermined specifications and storing parameters corresponding to the maximum temperature in a comparison circuit in the integrated circuit by selectively blowing fusable devices in the comparison circuit. The fusable devices may be antifuses.

Abstract: A method for storing a temperature threshold in an integrated circuit includes measuring operating parameters of the integrated circuit versus temperature, calculating a maximum temperature at which the integrated circuit performance exceeds predetermined specifications and storing parameters corresponding to the maximum temperature in a comparison circuit in the integrated circuit by selectively blowing fusable devices in the comparison circuit. The fusable devices may be antifuses.

Abstract: A semiconductor memory device (300) having a parallel test circuit is disclosed. A test data path (308) receives parallel I/O line (I/O0-I/O7) values, and generates therefrom test result data values (PASS and DATA_TST). The test result data values (PASS and DATA_TST) are coupled to a gate control circuit (312). The gate control circuit (312) provides either a first logic value, a second logic value, or an intermediate logic value to an open drain output driver (314) depending upon the test result data values (PASS and DATA_TST). In response to the logic values received from the gate control circuit (312), the open drain output driver (314) drives a data output (DQ) to a first, second or intermediate logic level.

Abstract: A method for storing a temperature threshold in an integrated circuit includes measuring operating parameters of the integrated circuit versus temperature, calculating a maximum temperature at which the integrated circuit performance exceeds predetermined specifications and storing parameters corresponding to the maximum temperature in a comparison circuit in the integrated circuit by selectively blowing fusable devices in the comparison circuit. The fusable devices may be antifuses. As a result, the integrated circuit is able to provide signals to devices external to the integrated circuit to indicate that the integrated circuit may be too hot to operate properly.

Abstract: A semiconductor memory device (300) having a parallel test circuit is disclosed. A test data path (308) receives parallel I/O line (I/O0-I/O7) values, and generates therefrom test result data values (PASS and DATA_TST). The test result data values (PASS and DATA_TST) are coupled to a gate control circuit (312). The gate control circuit (312) provides either a first logic value, a second logic value, or an intermediate logic value to an open drain output driver (314) depending upon the test result data values (PASS and DATA_TST). In response to the logic values received from the gate control circuit (312), the open drain output driver (314) drives a data output (DQ) to a first, second or intermediate logic level.

Abstract: A semiconductor memory device (300) having a parallel test circuit is disclosed. A test data path receives parallel I/O line (I/O0-I/O7) values, and generates therefrom test result data values (PASS and DATA_TST). The test result data values (PASS and DATA_TST) are coupled to a two-bit register (312) and output in a sequential fashion to an open drain output driver (314). In this manner, test result data values are provided by driving an output (DQ) in a rapid sequential fashion, rather than placing the output at one of three states (such as logic high state, a logic low state, or a high impedance state).

Abstract: A semiconductor memory device (300) having a parallel test circuit is disclosed. A test data path (308) receives parallel I/O line (I/O0-I/O7) values, and generates therefrom test result data values (PASS and DATA_TST). The test result data values (PASS and DATA_TST) are coupled to a gate control circuit (312). The gate control circuit (312) provides either a first logic value, a second logic value, or an intermediate logic value to an open drain output driver (314) depending upon the test result data values (PASS and DATA_TST). In response to the logic values received from the gate control circuit (312), the open drain output driver (314) drives a data output (DQ) to a first, second or intermediate logic level.

Abstract: A DRAM is disclosed that is capable of performing a rapid write-followed-by-read operation. In a preferred embodiment 400, the DRAM includes a plurality of memory banks (402-a402n), a global write bus (424), and a global read bus (426). The global write and read buses (424 and 426) are coupled to each memory bank (402a-402n) by an associated local read/write circuit (428a-428n). In an initial write operation to a first memory bank (402a-402n), input data on the global write bus (424) are latched in a first local read/write circuit (428a-428n) associated with the first memory bank (402a-402n). In a subsequent read operation to a second memory bank (402a-402n), as data are output from the second memory bank (402a-402n) onto the global read bus (426) via a second local read/write circuit (422a-422n), the first local/read write circuit (422a-422n) is simultaneously writing the latched input data into the first memory bank (402a-402n).

Abstract: A RAMBUS dynamic random access memory includes a test control circuit that selectively couples a row address latch to either a row sense control signal or a CMD control signal. In a normal operating mode, the test control circuit couples the row address latch to the row sense control signal so that the row sense control signal both latches a row address and senses a row of memory cells corresponding to the latched address. Prior to conducting a core noise test, the test control circuit couples the row address latch to the CMD control signal so that the row address is latched by the CMD control signal, and the row sense control signal only functions during the core noise test to sense a row corresponding to the latched row. The memory also includes a multiplexer that receives a time-multiplexed data/address bus and simultaneously couples a first part of the data/address bus to an internal data bus and a second part of the data/address bus to an internal address bus.

Abstract: A method for storing a temperature threshold in an integrated circuit includes measuring operating parameters of the integrated circuit versus temperature, calculating a maximum temperature at which the integrated circuit performance exceeds predetermined specifications and storing parameters corresponding to the maximum temperature in a comparison circuit in the integrated circuit by selectively blowing fusable devices in the comparison circuit. The fusable devices may be antifuses. As a result, the integrated circuit is able to provide signals to devices external to the integrated circuit to indicate that the integrated circuit may be too hot to operate properly.

Abstract: A method for storing a temperature threshold in an integrated circuit includes measuring operating parameters of the integrated circuit versus temperature, calculating a maximum temperature at which the integrated circuit performance exceeds predetermined specifications and storing parameters corresponding to the maximum temperature in a comparison circuit in the integrated circuit by selectively blowing fusable devices in the comparison circuit. The fusable devices may be antifuses. As a result, the integrated circuit is able to provide signals to devices external to the integrated circuit to indicate that the integrated circuit may be too hot to operate properly.

Abstract: A semiconductor memory (300) device having a redundancy test scheme is disclosed. A memory cell array (310) includes a normal section (312) and a redundant section (314, 316, and 318) of memory cells. In a normal mode of operation, the redundant section is selected if an applied address (ADD) corresponds to a defective bit in the normal section. In a redundant test mode of operation, the redundant section is selected based on a redundant test address (DFTRA, DFTCA). If the redundant test address is in the normal select logic level, a normal decode section (306 and 324) is selected. The redundant test address and a redundant test activation signal are applied to a redundant decoder (500). If the redundant test address is in a redundant select logic level and the redundant test activation signal is active, the redundant decoder is selectable based on the applied address value.

Abstract: A RAMBUS dynamic random access memory includes a test control circuit that selectively couples a row address latch to either a row sense control signal or a CMD control signal. In a normal operating mode, the test control circuit couples the row address latch to the row sense control signal so that the row sense control signal both latches a row address and senses a row of memory cells corresponding to the latched address. Prior to conducting a core noise test, the test control circuit couples the row address latch to the CMD control signal so that the row address is latched by the CMD control signal, and the row sense control signal only functions during the core noise test to sense a row corresponding to the latched row. The memory also includes a multiplexer that receives a time-multiplexed data/address bus and simultaneously couples a first part of the data/address bus to an internal data bus and a second part of the data/address bus to an internal address bus.

Abstract: A clock circuit including an input terminal (300) for receiving a clock signal and a first pulse generator (302) coupled to the input terminal. The first pulse generator is operable to generate a voltage pulse in response to a logic-low voltage to logic-high voltage transition of the clock signal. The circuit also includes a second pulse generator (304) coupled to the input terminal, the second pulse generator being operable to generate a voltage pulse in response to a logic-high voltage to logic-low voltage transition of the clock signal. A first clock deskewing circuit (306) is coupled between the first pulse generator and a first clock signal output terminal and a second clock deskewing circuit (308) is coupled between the second pulse generator and a second clock signal output terminal.

Abstract: A random access memory (RAM) (700) is disclosed which includes a reduced page size for decreasing power consumption, and a unique input/output (I/O) arrangement for maintaining a relatively large I/O space, without substantially increasing the number of I/O lines within the RAM. The RAM (700) includes a number banks (704) each of which is logically divided into even array sections and odd array sections (900). Data from the array sections (900) is coupled to I/O select blocks (914, 916, 918, 920) by groups of local I/O lines (902, 904, 906, 908). According to an applied address, the sense amplifiers within the even array sections are activated, indicating an "even" sense cycle, or the sense amplifiers within the odd array sections are activated, indicating an "odd" sense cycle. In an even sense cycle, the I/O select blocks (914, 916, 918, 920) couple the LIO line groups of the even array sections (900) to global I/O lines (910, 912).

Abstract: A clock circuit including a first delay circuit comprising an input terminal and a series of logic circuits, each of the logic circuits including an output terminal and first and second input terminals. The input terminal is coupled to the first input terminal of a first logic circuit in the series and the output of the first logic circuit is coupled to the second input terminal of a second logic circuit in the series. The output of the second logic circuit is coupled to the first input terminal of a third logic circuit in the series, and subsequent logic circuits in the series have alternately the first or second input terminal coupled to the output terminal of an immediately preceding logic circuit in the series. The circuit also includes a second delay circuit comprising an output terminal and a series of logic circuits, each of the logic circuits including an output terminal and first and second input terminals.

Abstract: Testing of an integrated circuit having arrays of memory cells occurs by writing to all of the arrays at the same time. Normal writing occurs only to one array. Additional test data bus leads on the chip carry test data signals from selected arrays to comparison circuits. The outputs of the comparison circuits flow to the output circuits of the chip. This achieves writing test data to four times the number of arrays as in a normal write and reading test data from twice the number of arrays as in a normal read operation.

Abstract: A system of interface circuits (15, 20-1 through 20-N) includes a mode sensing circuit (15) and one or more output circuits (20-1 through 20-N). The mode sensing circuit is arranged for producing control signals (on leads 22, 24) in response to an input signal (on lead 21). The output circuit (34-1) is arranged for producing an output data signal (DQ-1) dependent upon an input data signal (DATA) when the input signal (on lead 21) is in a first state and dependent upon the input data signal and the configuration of the connected output circuit (34-1) when the input signal is in a second state.

Abstract: An input circuit designed for a semiconductor device. A first input buffer (14) receives a control signal EN, an input signal IN, and a reference signal VREF, for producing a first output signal OUT.sub.1 in response the control signal and a difference between the input signal and the reference signal. A second input buffer (16) receives the control signal and the input signal, for producing a second output signal OUT.sub.2 in response to the control signal and the input signal. A control circuit (22) produces the control signal, in response to a predetermined output state.