Patents by Inventor Brian M. Czabaj
Brian M. Czabaj has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9006703Abstract: Aspects of the present invention relate to method for reducing lateral extrusion formed in semiconductor structures and semiconductor structures formed thereof. Various embodiments include a method for reducing lateral extrusion formed in semiconductor structures. The method can include removing a portion of a first lateral extrusion in an aluminum layer of the semiconductor structure, and determining a post-removal thickness of a dielectric layer positioned adjacent the aluminum layer. The post-removal thickness may be determined subsequent to the removing of the portion of the first lateral extrusion. The method can also include determining a difference between the post-removal thickness of the dielectric layer and a pre-removal thickness of the dielectric layer.Type: GrantFiled: July 31, 2013Date of Patent: April 14, 2015Assignee: International Business Machines CorporationInventors: Shawn A. Adderly, Brian M. Czabaj, Daniel A. Delibac, Jeffrey P. Gambino, Matthew D. Moon, David C. Thomas
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Publication number: 20150035117Abstract: Aspects of the present invention relate to method for reducing lateral extrusion formed in semiconductor structures and semiconductor structures formed thereof. Various embodiments include a method for reducing lateral extrusion formed in semiconductor structures. The method can include removing a portion of a first lateral extrusion in an aluminum layer of the semiconductor structure, and determining a post-removal thickness of a dielectric layer positioned adjacent the aluminum layer. The post-removal thickness may be determined subsequent to the removing of the portion of the first lateral extrusion. The method can also include determining a difference between the post-removal thickness of the dielectric layer and a pre-removal thickness of the dielectric layer.Type: ApplicationFiled: July 31, 2013Publication date: February 5, 2015Applicant: International Business Machines CorporationInventors: Shawn A. Adderly, Brian M. Czabaj, Daniel A. Delibac, Jeffrey P. Gambino, Matthew D. Moon, David C. Thomas
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Patent number: 8872289Abstract: Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes layering metal and insulator materials on a sacrificial material formed on a substrate. The method further includes masking the layered metal and insulator materials. The method further includes forming an opening in the masking which overlaps with the sacrificial material. The method further includes etching the layered metal and insulator materials in a single etching process to form the beam structure, such that edges of the layered metal and insulator material are aligned. The method further includes forming a cavity about the beam structure through a venting.Type: GrantFiled: February 4, 2013Date of Patent: October 28, 2014Assignee: International Business Machines CorporationInventors: Brian M. Czabaj, David A. DeMuynck, Anthony K. Stamper
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Patent number: 8691690Abstract: Disclosed are embodiments of a contact formation technique that incorporates a preventative etch step to reduce interlayer dielectric material flaking (e.g., borophosphosilicate glass (BPSG) flaking) and, thereby to reduce surface defects. Specifically, contact openings, which extend through a dielectric layer to semiconductor devices in and/or on a center portion of a substrate, can be filled with a conductor layer deposited by chemical vapor deposition (CVD). Chemical mechanical polishing (CMP) of the conductor layer can be performed to complete the contact structures. However, before the CMP process is performed (e.g., either before the contact openings are ever formed or before the contact openings are filled), a preventative etch process can be performed to remove any dielectric material from above the edge portion of the substrate. Removing the dielectric material from above the edge portion of the substrate prior to CMP reduces the occurrence of surface defects caused by dielectric material flaking.Type: GrantFiled: September 13, 2010Date of Patent: April 8, 2014Assignee: International Business Machines CorporationInventors: Yoba Amoah, Brian M. Czabaj, Thomas J. Dunbar, Jeffrey P. Gambino, Molly J. Leitch, Polina A. Razina
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Patent number: 8673670Abstract: Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes layering metal and insulator materials on a sacrificial material formed on a substrate. The method further includes masking the layered metal and insulator materials. The method further includes forming an opening in the masking which overlaps with the sacrificial material. The method further includes etching the layered metal and insulator materials in a single etching process to form the beam structure, such that edges of the layered metal and insulator material are aligned. The method further includes forming a cavity about the beam structure through a venting.Type: GrantFiled: December 15, 2011Date of Patent: March 18, 2014Assignee: International Business Machines CorporationInventors: Brian M. Czabaj, David A. DeMuynck, Anthony K. Stamper
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Patent number: 8658435Abstract: A method for forming a hydrogen barrier liner for a ferro-electric random access memory chip including forming a first dielectric layer over a substrate; forming a gate over the first dielectric layer; forming a first aluminum oxide layer over the gate and the first dielectric layer; forming a second dielectric layer over the first aluminum oxide layer; etching a trench through the second dielectric layer and the first aluminum oxide layer to the gate; forming a hydrogen barrier liner over the second dielectric layer, the hydrogen barrier liner lining the trench and contacting the gate; forming a silicon dioxide layer over the first aluminum dioxide layer, the silicon dioxide layer substantially filling the trench; and substantially removing the silicon dioxide layer leaving a silicon dioxide plug in the trench.Type: GrantFiled: January 23, 2013Date of Patent: February 25, 2014Assignee: International Business Machines CorporationInventors: Brian M. Czabaj, James V. Hart, III, William J. Murphy, James S. Nakos
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Publication number: 20130156993Abstract: Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes layering metal and insulator materials on a sacrificial material formed on a substrate. The method further includes masking the layered metal and insulator materials. The method further includes forming an opening in the masking which overlaps with the sacrificial material. The method further includes etching the layered metal and insulator materials in a single etching process to form the beam structure, such that edges of the layered metal and insulator material are aligned. The method further includes forming a cavity about the beam structure through a venting.Type: ApplicationFiled: December 15, 2011Publication date: June 20, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brian M. CZABAJ, David A. DeMUYNCK, Anthony K. STAMPER
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Patent number: 8395196Abstract: A ferro-electric random access memory (FRAM) chip, including a substrate; a first dielectric layer over the substrate; a gate over the first dielectric layer; a first aluminum oxide layer over the first dielectric layer and the gate; a second dielectric layer over the first aluminum oxide layer; a trench through the second dielectric layer and the first aluminum oxide layer to the gate; a hydrogen barrier liner over the second dielectric layer and lining the trench, and contacting the gate; and a silicon dioxide plug over the hydrogen barrier liner substantially filling the trench.Type: GrantFiled: November 16, 2010Date of Patent: March 12, 2013Assignee: International Business Machines CorporationInventors: Brian M. Czabaj, James V. Hart, III, William J. Murphy, James S. Nakos
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Publication number: 20120119273Abstract: A ferro-electric random access memory (FRAM) chip, including a substrate; a first dielectric layer over the substrate; a gate over the first dielectric layer; a first aluminum oxide layer over the first dielectric layer and the gate; a second dielectric layer over the first aluminum oxide layer; a trench through the second dielectric layer and the first aluminum oxide layer to the gate; a hydrogen barrier liner over the second dielectric layer and lining the trench, and contacting the gate; and a silicon dioxide plug over the hydrogen barrier liner substantially filling the trench.Type: ApplicationFiled: November 16, 2010Publication date: May 17, 2012Applicant: International Business Machines CorporationInventors: Brian M. Czabaj, James V. Hart, III, William J. Murphy, James S. Nakos
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Publication number: 20120064714Abstract: Disclosed are embodiments of a contact formation technique that incorporates a preventative etch step to reduce interlayer dielectric material flaking (e.g., borophosphosilicate glass (BPSG) flaking) and, thereby to reduce surface defects. Specifically, contact openings, which extend through a dielectric layer to semiconductor devices in and/or on a center portion of a substrate, can be filled with a conductor layer deposited by chemical vapor deposition (CVD). Chemical mechanical polishing (CMP) of the conductor layer can be performed to complete the contact structures. However, before the CMP process is performed (e.g., either before the contact openings are ever formed or before the contact openings are filled), a preventative etch process can be performed to remove any dielectric material from above the edge portion of the substrate. Removing the dielectric material from above the edge portion of the substrate prior to CMP reduces the occurrence of surface defects caused by dielectric material flaking.Type: ApplicationFiled: September 13, 2010Publication date: March 15, 2012Applicant: International Business Machines CorporationInventors: Yoba Amoah, Brian M. Czabaj, Thomas J. Dunbar, Jeffrey P. Gambino, Molly J. Leitch, Polina A. Razina
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Patent number: 8119754Abstract: Room temperature curing structural adhesive compositions including polyurethane oligomers having multi-methacrylate functionality, cycloalkylmethacrylate, at least one maleimide-functionalized compound and a cure system are disclosed. These compositions exhibit enhanced high temperature properties, including hot strength, heat/humidity strength, and heat aging strength, without compromising initial tensile strength and fixture speeds and still possessing a room temperature cure.Type: GrantFiled: December 8, 2009Date of Patent: February 21, 2012Assignee: Henkel CorporationInventors: Susan Lamtroung Levandoski, Christopher J. Verosky, Brian M. Czabaj
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Publication number: 20100084091Abstract: Room temperature curing structural adhesive compositions including polyurethane oligomers having multi-methacrylate functionality, cycloalkylmethacrylate, at least one maleimide-functionalized compound and a cure system are disclosed. These compositions exhibit enhanced high temperature properties, including hot strength, heat/humidity strength, and heat aging strength, without compromising initial tensile strength and fixture speeds and still possessing a room temperature cure.Type: ApplicationFiled: December 8, 2009Publication date: April 8, 2010Applicant: Henkel CorporationInventors: Susan Lamtroung Levandoski, Christopher J. Verosky, Brian M. Czabaj