Abstract: A device to create, receive, and transmit packets of data in a packet switching network. This device employs a direct memory access packet controller which would interface between memory contained within a computer system and a packet switched network. This direct memory access packet controller would utilize one or more micro-engines that would dynamically allocate buffer space to process received packets of data. This direct memory access packet controller would further utilize a transmit cell FIFO circuit to allocate buffer space to packets being transmitted. In addition, a sequencer would act to control the workflow of packets being received and transmitted.

Abstract: A device to create, receive, and transmit packets of data in a packet switching network. This device employs a direct memory access packet controller which would interface between memory contained within a computer system and a packet switched network. This direct memory access packet controller would utilize one or more micro-engines that would dynamically allocate buffer space to process received packets of data. This direct memory access packet controller would further utilize a transmit cell FIFO circuit to allocate buffer space to packets being transmitted. In addition, a sequencer would act to control the workflow of packets being received and transmitted.

Abstract: A test bus architecture for testing an integrated circuit having a plurality of agents includes providing both a test block select signal and test function select signal to a plurality of select decoders respectively disposed in each of the plurality of agents. The test block select signal has a number of states at least equal to the number of agents and the test function select signal at least equal to a maximum number of internal signal groups of any one of the agents, each select decoder having at least one internal signal group which is outputted from circuitry to be tested within the agent of the select decoder. An output from each of the select decoders is fed to a test bus output such that a selected internal signal group is outputted to the test bus output upon the agent of the selected signal group being selected by the state of the test block select signal and the selected signal group being selected by the state of the test function select signal by the select decoder.

Abstract: A host system is provided with one or more host-fabric adapters installed therein for connecting to a switched fabric of a data network.

Abstract: A host system is provided with one or more host-fabric adapters installed therein for connecting to a switched fabric of a data network. The host-fabric adapter may comprise at least one Micro-Engine arranged to establish connections and support data transfer operations, via a switched fabric, in response to work requests that cause instructions in a form of work queue elements “WQES” posted from a host system for said data transfer operations; and a work queue element “WQE” hardware assist “HWA” mechanism arranged to determine the starting address of each work queue element “WQE” based on queue pair (QP) context information needed for said Micro-Engine (ME) to process work requests for said data transfer operations.