Patents by Inventor Brian M. Shirley
Brian M. Shirley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7917692Abstract: A cache memory system and method includes a DRAM having a plurality of banks, and it also includes 2 SRAMs each having a capacity that is equal to the capacity of each bank of the DRAM. In operation, data read from a bank of the DRAM are stored in one of the SRAMs so that repeated hits to that bank are cached by reading from the SRAM. In the event of a write to a bank that is being refreshed, the write data are stored in one of the SRAMs. After the refresh of the bank has been completed, the data stored in the SRAM are transferred to the DRAM bank. A subsequent read or write to a second DRAM bank undergoing refresh and occurring during the transfer of data from an SRAM to the DRAM is stored in either the second bank or the other SRAM.Type: GrantFiled: February 12, 2008Date of Patent: March 29, 2011Assignee: Round Rock Research, LLCInventors: Brent Keeth, Brian M. Shirley, Charles H. Dennison, Kevin J. Ryan
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Publication number: 20100277964Abstract: A multi-bank memory device includes rows and columns of memory cores. Each row includes memory cores from one bank interleaved with memory cores from another bank. Banks in different rows can be simultaneously accessed.Type: ApplicationFiled: July 19, 2010Publication date: November 4, 2010Inventors: Brian M. Shirley, David R. Brown
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Patent number: 7760532Abstract: A multi-bank memory device includes rows and columns of memory cores. Each row includes memory cores from one bank interleaved with memory cores from another bank. Banks in different rows can be simultaneously accessed.Type: GrantFiled: September 26, 2007Date of Patent: July 20, 2010Assignee: Micron Technology, Inc.Inventors: Brian M. Shirley, David R. Brown
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Publication number: 20080177943Abstract: A cache memory system and method includes a DRAM having a plurality of banks, and it also includes 2 SRAMs each having a capacity that is equal to the capacity of each bank of the DRAM. In operation, data read from a bank of the DRAM are stored in one of the SRAMs so that repeated hits to that bank are cached by reading from the SRAM. In the event of a write to a bank that is being refreshed, the write data are stored in one of the SRAMs. After the refresh of the bank has been completed, the data stored in the SRAM are transferred to the DRAM bank. A subsequent read or write to a second DRAM bank undergoing refresh and occurring during the transfer of data from an SRAM to the DRAM is stored in either the second bank or the other SRAM.Type: ApplicationFiled: February 12, 2008Publication date: July 24, 2008Applicant: Micron Technology, Inc.Inventors: Brent Keeth, Brian M. Shirley, Charles H. Dennison, Kevin J. Ryan
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Patent number: 7350018Abstract: A cache memory system and method includes a DRAM having a plurality of banks, and it also includes 2 SRAMs each having a capacity that is equal to the capacity of each bank of the DRAM. In operation, data read from a bank of the DRAM are stored in one of the SRAMs so that repeated hits to that bank are cached by reading from the SRAM. In the event of a write to a bank that is being refreshed, the write data are stored in one of the SRAMs. After the refresh of the bank has been completed, the data stored in the SRAMs are transferred to the DRAM bank. A subsequent read or write to a second DRAM bank undergoing refresh and occurring during the transfer of data from an SRAM to the DRAM is stored in either the second bank or the other SRAM.Type: GrantFiled: November 8, 2006Date of Patent: March 25, 2008Assignee: Micron Technology, Inc.Inventors: Brent Keeth, Brian M. Shirley, Charles H. Dennison, Kevin J. Ryan
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Patent number: 7292497Abstract: A multi-bank memory device includes rows and columns of memory cores. Each row includes memory cores from one bank interleaved with memory cores from another bank. Banks in different rows can be simultaneously accessed.Type: GrantFiled: April 18, 2006Date of Patent: November 6, 2007Assignee: Micron Technology, Inc.Inventors: Brian M. Shirley, David R. Brown
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Patent number: 7155561Abstract: A cache memory system and method includes a DRAM having a plurality of banks, and it also includes 2 SRAMs each having a capacity that is equal to the capacity of each bank of the DRAM. In operation, data read from a bank of the DRAM are stored in one of the SRAMs so that repeated hits to that bank are cached by reading from the SRAM. In the event of a write to a bank that is being refreshed, the write data are stored in one of the SRAMs. After the refresh of the bank has been completed, the data stored in the SRAM are transferred to the DRAM bank. A subsequent read or write to a second DRAM bank undergoing refresh and occurring during the transfer of data from an SRAM to the DRAM is stored in either the second bank or the other SRAM.Type: GrantFiled: September 19, 2005Date of Patent: December 26, 2006Assignee: Micron Technology, Inc.Inventors: Brent Keeth, Brian M. Shirley, Charles H. Dennison
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Patent number: 7106637Abstract: An asynchronous address interface circuit and method for converting unrestricted randomly scheduled address transitions of memory address signals into scheduled address events from which initiation of a sequence of memory access events can be based. The address interface circuit initiates a delay sequence based on a address transition detection pulse. In the event a new address transition detection pulse is received prior to completion of the delay sequence, the delay sequence is reset and restarted based on the new address transition detection pulse. The sequence of memory access events is initiated in response to the completion of the delay sequence.Type: GrantFiled: January 8, 2004Date of Patent: September 12, 2006Assignee: Micron Technology, Inc.Inventors: Simon J. Lovett, Cliff Zitlaw, Brian M. Shirley, Roger D. Norwood, John F. Schreck
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Patent number: 7088604Abstract: A multi-bank memory device includes rows and columns of memory cores. Each row includes memory cores from one bank interleaved with memory cores from another bank. Banks in different rows can be simultaneously accessed.Type: GrantFiled: March 15, 2001Date of Patent: August 8, 2006Assignee: Micron Technology, Inc.Inventors: Brian M. Shirley, David R. Brown
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Patent number: 7079439Abstract: A power saving circuit disables input buffers for command and address signals during an auto-refresh of a DRAM. The input buffers are re-enabled at the end of the auto-refresh in a manner that does not cause spurious commands to be generated. The power saving circuit prevents spurious commands by biasing internal command signals to a “no operation” command whenever the input buffers for the command signals are disabled. The DRAM may also be placed in a mode in which it automatically transitions to a low power precharge mode at the end of the auto-refresh to further reduce power consumed by the DRAM.Type: GrantFiled: June 14, 2004Date of Patent: July 18, 2006Assignee: Micron Technology, Inc.Inventors: Timothy B. Cowles, Brian M. Shirley, Greg A. Blodgett
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Patent number: 6965536Abstract: A DRAM includes a set of secondary sense amplifiers as well as primary sense amplifiers coupled to respective digit lines of a DRAM array. The secondary sense amplifiers are coupled to the digit lines of an array through isolation transistors so that the secondary sense amplifier can be selectively isolated from the digit lines of an array. The DRAM also includes a refresh controller that periodically refreshes the DRAM on a row-by-row basis, and a command decoder that causes the refresh to be aborted in the even a read or a write command is received by the DRAM during a refresh. The refresh is aborted by saving the data stored in the row being refreshed in the secondary sense amplifiers and then isolating the sense amplifiers from the array. The memory access is then implemented in a normal manner. Since the DRAM can be accessed without waiting for the completion of a refresh in progress, the DRAM can be used as a cache memory in a computer system.Type: GrantFiled: August 5, 2004Date of Patent: November 15, 2005Assignee: Micron Technology, Inc.Inventor: Brian M. Shirley
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Patent number: 6948027Abstract: A cache memory system and method includes a DRAM having a plurality of banks, and it also includes 2 SRAMs each having a capacity that is equal to the capacity of each bank of the DRAM. In operation, data read from a bank of the DRAM are stored in one of the SRAMs so that repeated hits to that bank are cached by reading from the SRAM. In the event of a write to a bank that is being refreshed, the write data are stored in one of the SRAMs. After the refresh of the bank has been completed, the data stored in the SRAM are transferred to the DRAM bank. A subsequent read or write to a second DRAM bank undergoing refresh and occurring during the transfer of data from an SRAM to the DRAM is stored in either the second bank or the other SRAM.Type: GrantFiled: March 30, 2004Date of Patent: September 20, 2005Assignee: Micron Technology, Inc.Inventors: Brent Keeth, Brian M. Shirley, Charles H. Dennison, Kevin J. Ryan
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Patent number: 6937536Abstract: A fuse option for a dynamic random access memory (DRAM) is provided to selectively slow row address signals when redundant rows of memory cells have been selected for use. The fuse option is blown when a redundant row is used to replace a defective row as identified during manufacture of a DRAM. The fuse is coupled to delay circuitry which has a known delay. When the fuse is blown after detecting a defective row, the delay circuitry is coupled in series with selected portions of a row address strobe (RAS) chain of circuitry used to propagate row address selection signals to the proper rows. This provides extra time needed for row address compare and override circuitry, which is not in series with the delay circuitry.Type: GrantFiled: September 17, 2003Date of Patent: August 30, 2005Assignee: Micron Technology, Inc.Inventor: Brian M. Shirley
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Patent number: 6862654Abstract: A cache memory system and method includes a DRAM having a plurality of banks, and it also includes 2 SRAMs each having a capacity that is equal to the capacity of each bank of the DRAM. In operation, data read from a bank of the DRAM are stored in one of the SRAMs so that repeated hits to that bank are cached by reading from the SRAM. In the event of a write to a bank that is being refreshed, the write data are stored in one of the SRAMs. After the refresh of the bank has been completed, the data stored in the SRAM are transferred to the DRAM bank. A subsequent read or write to a second DRAM bank undergoing refresh and occurring during the transfer of data from an SRAM to the DRAM is stored in either the second bank or the other SRAM.Type: GrantFiled: August 17, 2000Date of Patent: March 1, 2005Assignee: Micron Technology, Inc.Inventors: Brent Keeth, Brian M. Shirley, Charles H. Dennison, Kevin J. Ryan
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Publication number: 20040268018Abstract: A power saving circuit disables input buffers for command and address signals during an auto-refresh of a DRAM. The input buffers are re-enabled at the end of the auto-refresh in a manner that does not cause spurious commands to be generated. The power saving circuit prevents spurious commands by biasing internal command signals to a “no operation” command whenever the input buffers for the command signals are disabled. The DRAM may also be placed in a mode in which it automatically transitions to a low power precharge mode at the end of the auto-refresh to further reduce power consumed by the DRAM.Type: ApplicationFiled: June 14, 2004Publication date: December 30, 2004Inventors: Timothy B. Cowles, Brian M. Shirley, Greg A. Blodgett
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Publication number: 20040186957Abstract: A cache memory system and method includes a DRAM having a plurality of banks, each of which may be refreshed under control of a refresh controller. In addition to the usual components of a DRAM, the cache memory system also includes 2 SRAMs each having a capacity that is equal to the capacity of each bank of the DRAM. In operation, data read from a bank of the DRAM are stored in one of the SRAMs so that repeated hits to that bank are cached by reading from the SRAM. In the event of a write to a bank that is being refreshed, the write data are stored in one of the SRAMs. After the refresh of the bank has been completed, the data stored in the SRAM are transferred to the DRAM bank. A subsequent read or write to a second DRAM bank undergoing refresh and occurring during the transfer of data from an SRAM to the DRAM is stored in the second bank. If, however, the second bank is being refreshed, the data are stored in the other SRAM.Type: ApplicationFiled: March 30, 2004Publication date: September 23, 2004Inventors: Brent Keeth, Brian M. Shirley, Charles H. Dennison
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Patent number: 6778453Abstract: A method for storing a temperature threshold in an integrated circuit includes measuring operating parameters of the integrated circuit versus temperature, calculating a maximum temperature at which the integrated circuit performance exceeds predetermined specifications and storing parameters corresponding to the maximum temperature in a comparison circuit in the integrated circuit by selectively blowing fusable devices in the comparison circuit. The fusable devices may be antifuses.Type: GrantFiled: February 24, 2003Date of Patent: August 17, 2004Assignee: Micron Technology, Inc.Inventors: Christopher B. Cooper, Ming-Bo Liu, Chris G. Martin, Troy A. Manning, Stephen L. Casper, Charles H. Dennison, Brian M. Shirley, Brian L. Brown, Shubneesh Batra
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Patent number: 6779076Abstract: A DRAM includes a set of secondary sense amplifiers as well as primary sense amplifiers coupled to respective digit lines of a DRAM array. The secondary sense amplifiers are coupled to the digit lines of an array through isolation transistors so that the secondary sense amplifier can be selectively isolated from the digit lines of an array. The DRAM also includes a refresh controller that periodically refreshes the DRAM on a row-by-row basis, and a command decoder that causes the refresh to be aborted in the even a read or a write command is received by the DRAM during a refresh. The refresh is aborted by saving the data stored in the row being refreshed in the secondary sense amplifiers and then isolating the sense amplifiers from the array. The memory access is then implemented in a normal manner. Since the DRAM can be accessed without waiting for the completion of a refresh in progress, the DRAM can be used as a cache memory in a computer system.Type: GrantFiled: October 5, 2000Date of Patent: August 17, 2004Assignee: Micron Technology, Inc.Inventor: Brian M. Shirley
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Patent number: 6771553Abstract: A power saving circuit disables input buffers for command and address signals during an auto-refresh of a DRAM. The input buffers are re-enabled at the end of the auto-refresh in a manner that does not cause spurious commands to be generated. The power saving circuit prevents spurious commands by biasing internal command signals to a “no operation” command whenever the input buffers for the command signals are disabled. The DRAM may also be placed in a mode in which it automatically transitions to a low power precharge mode at the end of the auto-refresh to further reduce power consumed by the DRAM.Type: GrantFiled: October 18, 2001Date of Patent: August 3, 2004Assignee: Micron Technology, Inc.Inventors: Timothy B. Cowles, Brian M. Shirley, Greg A. Blodgett
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Publication number: 20040141397Abstract: An asynchronous address interface circuit and method for converting unrestricted randomly scheduled address transitions of memory address signals into scheduled address events from which initiation of a sequence of memory access events can be based. The address interface circuit initiates a delay sequence based on a address transition detection pulse. In the event a new address transition detection pulse is received prior to completion of the delay sequence, the delay sequence is reset and restarted based on the new address transition detection pulse. The sequence of memory access events is initiated in response to the completion of the delay sequence.Type: ApplicationFiled: January 8, 2004Publication date: July 22, 2004Inventors: Simon J. Lovett, Cliff Zitlaw, Brian M. Shirley, Roger D. Norwood, John F. Schreck