Patents by Inventor Brian Mitchell Bass
Brian Mitchell Bass has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9448846Abstract: A computer system having a plurality of processing resources, including a sub-system for scheduling and dispatching processing jobs to a plurality of hardware accelerators, the subsystem further comprising a job requestor, for requesting jobs having bounded and varying latencies to be executed on the hardware accelerators; a queue controller to manage processing job requests directed to a plurality of hardware accelerators; and multiple hardware queues for dispatching jobs to the plurality of hardware acceleration engines, each queue having a dedicated head of queue entry, dynamically sharing a pool of queue entries, having configurable queue depth limits, and means for removing one or more jobs across all queues.Type: GrantFiled: December 13, 2011Date of Patent: September 20, 2016Assignee: International Business Machines CorporationInventors: Brian Mitchell Bass, Bartholomew Blaner, George William Daly, Jr., Jeffrey Haskell Derby, Ross Boyd Leavens, Joseph Gerald McDonald
-
Patent number: 9286129Abstract: A system and method of terminating processing requests dispatched to a coprocessor hardware accelerator in a multi-processor computer system based on matching various fields in the request made to the coprocessor to identify the process to be terminated. A kill command is initiated by a write operation to a coprocessor block kill register and has match enable and value for each field in the coprocessor request to be terminated. Enabled fields may have one or more values associated with a single request or multiple requests for the same coprocessor. At least one match enable must be set to initiate a kill request. A process kill active signal prevents other coprocessor jobs from moving between operational stages in the coprocessor hardware accelerator. Processing jobs that are idle or do not match the fields with match enables set signal done with no match and continue processing. Processing jobs that do match the fields with match enables set are terminated and signal done with match.Type: GrantFiled: May 8, 2013Date of Patent: March 15, 2016Assignee: International Business Machines CorporationInventors: Brian Mitchell Bass, Bartholomew Blaner, Jay Gerald Heaslip, Robert Dov Herzl, Kenneth Anthony Lauricella, Ross Boyd Leavens
-
Patent number: 9251108Abstract: A structure and method of allocating read buffers among multiple bus agents requesting read access in a multi-processor computer system. The number of outstanding reads a requestor may have based on the current function it is executing is dynamically limited, instead of based on local buffer space available or a fixed allocation, which improves the overall bandwidth of the requestors sharing the buffers. A requesting bus agent may control when read data may be returned from shared buffers to minimize the amount of local buffer space allocated for each requesting agent, while maintaining high bandwidth output for local buffers. Requests can be made for virtual buffers by oversubscribing the physical buffers and controlling the return of read data to the buffers.Type: GrantFiled: November 5, 2012Date of Patent: February 2, 2016Assignee: International Business Machines CorporationInventors: Brian Mitchell Bass, Kenneth Anthony Lauricella
-
Publication number: 20140129749Abstract: A structure and method of allocating read buffers among multiple bus agents requesting read access in a multi-processor computer system. The number of outstanding reads a requestor may have based on the current function it is executing is dynamically limited, instead of based on local buffer space available or a fixed allocation, which improves the overall bandwidth of the requestors sharing the buffers. A requesting bus agent may control when read data may be returned from shared buffers to minimize the amount of local buffer space allocated for each requesting agent, while maintaining high bandwidth output for local buffers. Requests can be made for virtual buffers by oversubscribing the physical buffers and controlling the return of read data to the buffers.Type: ApplicationFiled: November 5, 2012Publication date: May 8, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brian Mitchell Bass, Kenneth Anthony Lauricella
-
Publication number: 20130304990Abstract: Selective cache injection of write data generated or used by a coprocessor hardware accelerator in a multi-core processor system having a hierarchical bus architecture to facilitate transfer of address and data between multiple agents coupled to the bus. A bridge device maintains configuration settings for cache injection of write data and includes a set of n shared write data buffers used for write requests to memory. Each coprocessor hardware accelerator has m local write data cacheline buffers holding different types of write data. For write data produced by a coprocessor hardware accelerator, cache injection is accomplished based on configuration settings in a DMA channel dedicated to the coprocessor and a bridge controller. The access history of cache injected data for a particular processing thread or data flow is also tracked to determine whether to down grade or maintain a request for cache injection.Type: ApplicationFiled: May 8, 2012Publication date: November 14, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brian Mitchell BASS, Kenneth Anthony LAURICELLA, Ross Boyd LEAVENS
-
Publication number: 20130152099Abstract: A computer system having a plurality of processing resources, including a sub-system for scheduling and dispatching processing jobs to a plurality of hardware accelerators, the subsystem further comprising a job requestor, for requesting jobs having bounded and varying latencies to be executed on the hardware accelerators; a queue controller to manage processing job requests directed to a plurality of hardware accelerators; and multiple hardware queues for dispatching jobs to the plurality of hardware acceleration engines, each queue having a dedicated head of queue entry, dynamically sharing a pool of queue entries, having configurable queue depth limits, and means for removing one or more jobs across all queues.Type: ApplicationFiled: December 13, 2011Publication date: June 13, 2013Applicant: International Business Machines CorporationInventors: Brian Mitchell Bass, Bartholomew Blaner, George William Daly, JR., Jeffrey Haskell Derby, Ross Boyd Leavens, Joseph Gerald McDonald
-
Patent number: 8281075Abstract: A technique for triggering a system bus write command with user code includes identifying a specific store-type instruction in a user instruction sequence. The specific store-type instruction is converted into a specific request-type command, which is configured to include core permission controls (that are stored in core configuration registers of a processor core by a trusted kernel) and user created data (stored in a cache memory). Slave devices are configured through register space (that is only accessible by the trusted kernel) with respective slave permission controls. The specific request-type command is then transmitted from the cache memory, via a system bus. In this case, the slave devices that receive the specific request-type command process the specific request-type command when the core permission controls are the same as the respective slave permission controls. The trusted kernel may be included in a hypervisor or an operating system.Type: GrantFiled: April 14, 2009Date of Patent: October 2, 2012Assignee: International Business Machines CorporationInventors: Lakshminarayana Baba Arimilli, Brian Mitchell Bass, David Wayne Cummings, Bernard Charles Drerup, Guy Lynn Guthrie, Ronald Nick Kalla, Hugh Shen, Michael Steven Siegel, William John Starke, Derek Edward Williams
-
Patent number: 8244911Abstract: A method for decompressing multiple data streams includes receiving a packet of data of a compressed data stream, directing the received packet to a selected one of a plurality of decompression functional units within a hardware-based decompression accelerator unit, obtaining decompression state information pertaining to the compressed data stream, and decompressing the received packet using the obtained decompression state information.Type: GrantFiled: July 22, 2008Date of Patent: August 14, 2012Assignee: International Business Machines CorporationInventors: Brian Mitchell Bass, Giora Biran, Hubertus Franke, Hao Yu
-
Patent number: 8130650Abstract: The decision within a packet processing device to transmit a newly arriving packet into a queue to await further processing or to discard the same packet is made by a flow control method and system. The flow control is updated with a constant period determined by storage and flow rate limits. The update includes comparing current queue occupancy to a threshold. The outcome of the update is adjustment up or down of the transmit probability value. The value is stored for the subsequent period of flow control and packets arriving during that period are subject to a transmit or discard decision that uses that value.Type: GrantFiled: July 17, 2008Date of Patent: March 6, 2012Assignee: International Business Machines CorporationInventors: James Johnson Allen, Jr., Brian Mitchell Bass, Gordon Taylor Davis, Clark Debs Jeffries, Jitesh Ramachandran Nair, Ravinder Kumar Sabhikhi, Michael Steven Siegel, Rama Mohan Yedavalli
-
Patent number: 7984038Abstract: Novel data structures, methods and apparatus for finding the longest prefix match search when searching tables with variable length patterns or prefixes. To find the exact match or the best matching prefix, patterns have to be compared a bit at a time until the exact or first match is found. This requires “n” number of comparisons or memory accesses to identify the closest matching pattern. The trees are built in such a way that the matching result is guaranteed to be a best match, whether it is an exact match or a longest prefix match. Using the trail of all the birds and associated prefix lengths enables determination of the correct prefix result from the trail. By construction, the search tree provides the best matching prefix at or after the first compare during walking of the trail or tree.Type: GrantFiled: April 15, 2008Date of Patent: July 19, 2011Assignee: International Business Machines CorporationInventors: Brian Mitchell Bass, Jean Louis Calvignac, Marco C. Heddes, Antonios Maragkos, Piyush Chunilal Patel, Michael Steven Siegel, Fabrice Jean Verplanken
-
Patent number: 7818509Abstract: A cache coherency technique used in a multi-node symmetric multi-processor system that reduces the number of message phases of a read request from 5 to 4, canceling the combined response phase for read requests in most cases, thereby improving system performance and reducing the overall system power consumption.Type: GrantFiled: October 31, 2007Date of Patent: October 19, 2010Assignee: International Business Machines CorporationInventors: Brian Mitchell Bass, Eric Francis Robinson, Thuong Quang Truong
-
Publication number: 20100262735Abstract: A technique for triggering a system bus write command with user code includes identifying a specific store-type instruction in a user instruction sequence. The specific store-type instruction is converted into a specific request-type command, which is configured to include core permission controls (that are stored in core configuration registers of a processor core by a trusted kernel) and user created data (stored in a cache memory). Slave devices are configured through register space (that is only accessible by the trusted kernel) with respective slave permission controls. The specific request-type command is then transmitted from the cache memory, via a system bus. In this case, the slave devices that receive the specific request-type command (via the system bus) process the specific request-type command when the core permission controls are the same as the respective slave permission controls.Type: ApplicationFiled: April 14, 2009Publication date: October 14, 2010Applicant: INTERNATIONAL BUISNESS MACHINES CORPORATIONInventors: Lakshminarayana Baba Arimilli, Brian Mitchell Bass, David Wayne Cummings, Bernard Charles Drerup, Guy Lynn Guthrie, Ronald Nick Kalla, Hugh Shen, Michael Steven Siegel, William John Starke, Derek Edward Williams
-
Publication number: 20100020825Abstract: A method for decompressing multiple data streams includes receiving a packet of data of a compressed data stream, directing the received packet to a selected one of a plurality of decompression functional units within a hardware-based decompression accelerator unit, obtaining decompression state information pertaining to the compressed data stream, and decompressing the received packet using the obtained decompression state information.Type: ApplicationFiled: July 22, 2008Publication date: January 28, 2010Inventors: Brian Mitchell Bass, Giora Biran, Hubertus Franke, Hao Yu
-
Patent number: 7620048Abstract: An apparatus is disclosed for transporting control information in a communications system. The apparatus comprises a network processor, a control point processor operatively coupled to the network processor, and a guided frame generated by the control point processor. The guided frame comprises a first section in which frame control information is placed and is used by the network processor to update at least one control register within the network processor; a second section carrying correlators assigned by the control point processor to correlate guided frame responses with their requests; a third section carrying one or a sequence of guided commands; and an End delimiter guided command.Type: GrantFiled: June 14, 2005Date of Patent: November 17, 2009Assignee: International Business Machines CorporationInventors: Brian Mitchell Bass, Jean Louis Calvignac, Anthony Matteo Gallo, Marco C. Heddes, Sridhar Rao, Michael Steven Siegel, Brian Alan Youngman, Fabrice Jean Verplanken
-
Patent number: 7590057Abstract: A control sub system, a plurality of interface processors, a plurality of media interfaces a plurality of queues are operatively coupled and responsive to a control signal to move data from a memory to a selected one of the plurality of queues.Type: GrantFiled: June 14, 2005Date of Patent: September 15, 2009Assignee: International Business Machines CorporationInventors: Brian Mitchell Bass, Jean Louis Calvignac, Anthony Matteo Gallo, Marco C. Heddes, Sridhar Rao, Michael Steven Siegel, Brian Alan Youngman, Fabrice Jean Verplanken
-
Publication number: 20090113138Abstract: A cache coherency technique used in a multi-node symmetric multi-processor system that reduces the number of message phases of a read request from 5 to 4, canceling the combined response phase for read requests in most cases, thereby improving system performance and reducing the overall system power consumption.Type: ApplicationFiled: October 31, 2007Publication date: April 30, 2009Inventors: Brian Mitchell Bass, Eric Francis Robinson, Thuong Quang Truong
-
Publication number: 20080273464Abstract: The decision within a packet processing device to transmit a newly arriving packet into a queue to await further processing or to discard the same packet is made by a flow control method and system. The flow control is updated with a constant period determined by storage and flow rate limits. The update includes comparing current queue occupancy to a threshold. The outcome of the update is adjustment up or down of the transmit probability value. The value is stored for the subsequent period of flow control and packets arriving during that period are subject to a transmit or discard decision that uses that value.Type: ApplicationFiled: July 17, 2008Publication date: November 6, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James Johnson Allen, Brian Mitchell Bass, Gordon Taylor Davis, Clark Debs Jeffries, Jitesh Ramachandran Nair, Ravinder Kumar Sabhikhi, Michael Steven Siegel, Rama Mohan Yedavalli
-
Patent number: 7430169Abstract: The decision within a packet processing device to transmit a newly arriving packet into a queue to await further processing or to discard the same packet is made by a flow control method and system. The flow control is updated with a constant period determined by storage and flow rate limits. The update includes comparing current queue occupancy to a threshold. The outcome of the update is adjustment up or down of the transmit probability value. The value is stored for the subsequent period of flow control and packets arriving during that period are subject to a transmit or discard decision that uses that value.Type: GrantFiled: June 3, 2002Date of Patent: September 30, 2008Assignee: International Business Machines CorporationInventors: James Johnson Allen, Jr., Brian Mitchell Bass, Gordon Taylor Davis, Clark Debs Jeffries, Jitesh Ramachandran Nair, Ravinder Kumar Sabhikhi, Michael Steven Siegel, Rama Mohan Yedavalli
-
Publication number: 20080222116Abstract: Novel data structures, methods and apparatus for finding the longest prefix match search when searching tables with variable length patterns or prefixes. To find the exact match or the best matching prefix, patterns have to be compared a bit at a time until the exact or first match is found. This requires “n” number of comparisons or memory accesses to identify the closest matching pattern. The trees are built in such a way that the matching result is guaranteed to be a best match, whether it is an exact match or a longest prefix match. Using the trail of all the birds and associated prefix lengths enables determination of the correct prefix result from the trail. By construction, the search tree provides the best matching prefix at or after the first compare during walking of the trail or tree.Type: ApplicationFiled: April 15, 2008Publication date: September 11, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brian Mitchell Bass, Jean Louis Calvignac, Marco C. Heddes, Antonios Maragkos, Piyush Chunilal Patel, Michael Steven Siegel, Fabrice Jean Verplanken
-
Patent number: 7383244Abstract: Novel data structures, methods and apparatus for finding the longest prefix match search when searching tables with variable length patterns or prefixes. To find the exact match or the best matching prefix, patterns have to be compared a bit at a time until the exact or first: match is found. This requires “n” number of comparisons or memory accesses to identify the closest matching pattern. The trees are built in such a way that the matching result is guaranteed to be a best match, whether it is an exact match or a longest prefix match. Using the trail of all the birds and associated prefix lengths enables determination of the correct prefix result from the trail. By construction, the search tree provides the best matching prefix at or after the first compare during walking of the trail or tree.Type: GrantFiled: January 28, 2005Date of Patent: June 3, 2008Assignee: International Business Machines CorporationInventors: Brian Mitchell Bass, Jean Louis Calvignac, Marco C. Heddes, Antonios Maragkos, Piyush Chunilal Patel, Michael Steven Siegel, Fabrice Jean Verplanken