Abstract: A method of electronically administering instructions, includes receiving a new instruction; creating new instruction metadata from the new instruction; comparing the new instruction metadata to a data set of existing instruction metadata to identify existing instructions corresponding to the new instruction; determining whether the new instruction metadata indicates that the new instruction revises an existing instruction; comparing the new instruction to any corresponding existing instructions, where the new copy instruction metadata does not indicate that the new instruction revises an existing instruction, to determine if the new instruction revises the existing instructions; initiating revision workflow where the new instruction is determined to revise an existing instruction; and storing the new instruction metadata in the data set of existing instruction metadata and the new instruction in a corresponding data set of existing instructions.

Abstract: A method of electronically administering instructions, includes receiving a new instruction; creating new instruction metadata from the new instruction; comparing the new instruction metadata to a data set of existing instruction metadata to identify existing instructions corresponding to the new instruction; determining whether the new instruction metadata indicates that the new instruction revises an existing instruction; comparing the new instruction to any corresponding existing instructions, where the new copy instruction metadata does not indicate that the new instruction revises an existing instruction, to determine if the new instruction revises the existing instructions; initiating revision workflow where the new instruction is determined to revise an existing instruction; and storing the new instruction metadata in the data set of existing instruction metadata and the new instruction in a corresponding data set of existing instructions.

Abstract: A data processing circuit (201) is shown having elements (315, 310) which operate in response to decoded instruction while receiving clocking signals. Instruction types are identified and clocking signals to at least one of the elements is enabled or disabled in dependence upon whether the element is required for the execution of the identified instruction type.

Abstract: A data processing circuit is arranged to execute program instructions defining nested loops. A loop is defined in terms of a start address, an end address and a number of loop iterations. The processing circuit includes a program counter and a plurality of loop counting elements. Each of the loop counting elements includes a start address register, an end address register, a loop iteration register and means for comparing the value stored in the respective end address register with the output from the program counter.

Abstract: A data processing circuit includes a first set of processing elements and a second set of processing elements. A clock provides common clocking signals to the processing elements, however, the first set of elements are clocked by rising edges of the clocking signals and the second set of elements are clocked by falling edges of the clocking signals.