Patents by Inventor Brian Patrick Towles
Brian Patrick Towles has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240169124Abstract: Improvements in a molecular-dynamic simulator provide ways to save energy during computation and reduce die area consumed on an integrated circuit. Examples of such improvements include different interaction modules for different ranges, the use of streaming along rows while multicasting along columns in an array of interaction modules, the selection of computation units based on balancing computational costs and communication costs, the use of fences in networks that connect computation units, and the use of bond calculators to carry out specialized bond calculations.Type: ApplicationFiled: March 18, 2022Publication date: May 23, 2024Inventors: Brannon Batson, Brian Lee Greskamp, Bruce Edwards, Jeffrey Adam Butts, Christopher Howard Fenton, Jeffrey Paul Grossman, Douglas John Ierardi, Adam Lerer, Brian Patrick Towles, Michael Edmund Bergdorf, Cristian Predescu, John K. Salmon, Andrew Garvin Taube
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Publication number: 20240137308Abstract: Systems and method for routing data packets in ring network. A data packet being transmitted to a destination node may be received by a first structure at a first node. The first node may determine a number of hops the data packet will traverse as it is transmitted from the first node to the destination node and compare the determined number of hops to a threshold hop value to determine whether the number of hops is equal to or less than the threshold hop value. If the number of hops is greater than the threshold, the data packet may be transmitted to a dimension queuing structure for a first virtual channel within a second node, otherwise, the data packet may be transmitted to a dimension queuing structure for a second virtual channel or a turn queuing structure within the second node.Type: ApplicationFiled: October 14, 2022Publication date: April 25, 2024Inventors: Brian Patrick Towles, Hojat Parta
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Publication number: 20230094933Abstract: Methods, systems, and apparatus, including computer programs encoded on computer-storage media, for connecting processors using twisted torus configurations. In some implementations, a cluster of processing nodes is coupled using a reconfigurable interconnect fabric. The system determines a number of processing nodes to allocate as a network within the cluster and a topology for the network. The system selects an interconnection scheme for the network, where the interconnection scheme is selected from a group that includes at least a torus interconnection scheme and a twisted torus interconnection scheme. The system allocates the determined number of processing nodes of the cluster in the determined topology, sets the reconfigurable interconnect fabric to provide the selected interconnection scheme for the processing nodes in the network, and provides access to the network for performing a computing task.Type: ApplicationFiled: November 28, 2022Publication date: March 30, 2023Inventor: Brian Patrick Towles
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Patent number: 11516087Abstract: Methods, systems, and apparatus, including computer programs encoded on computer-storage media, for connecting processors using twisted torus configurations. In some implementations, a cluster of processing nodes is coupled using a reconfigurable interconnect fabric. The system determines a number of processing nodes to allocate as a network within the cluster and a topology for the network. The system selects an interconnection scheme for the network, where the interconnection scheme is selected from a group that includes at least a torus interconnection scheme and a twisted torus interconnection scheme. The system allocates the determined number of processing nodes of the cluster in the determined topology, sets the reconfigurable interconnect fabric to provide the selected interconnection scheme for the processing nodes in the network, and provides access to the network for performing a computing task.Type: GrantFiled: December 11, 2020Date of Patent: November 29, 2022Assignee: Google LLCInventor: Brian Patrick Towles
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Publication number: 20220173973Abstract: Methods, systems, and apparatus, including computer programs encoded on computer-storage media, for connecting processors using twisted torus configurations. In some implementations, a cluster of processing nodes is coupled using a reconfigurable interconnect fabric. The system determines a number of processing nodes to allocate as a network within the cluster and a topology for the network. The system selects an interconnection scheme for the network, where the interconnection scheme is selected from a group that includes at least a torus interconnection scheme and a twisted torus interconnection scheme. The system allocates the determined number of processing nodes of the cluster in the determined topology, sets the reconfigurable interconnect fabric to provide the selected interconnection scheme for the processing nodes in the network, and provides access to the network for performing a computing task.Type: ApplicationFiled: December 11, 2020Publication date: June 2, 2022Inventor: Brian Patrick Towles
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Patent number: 9906467Abstract: A data communication apparatus includes a router, first and second packet producers, and a penalizer. The router is directly connected to the first and second producers. The penalizer assesses penalties against each producer whenever that producer is serviced. The penalty value depends at least in part on an expected extent to which the first producer requires service. The penalizer then accumulates penalties against each producer.Type: GrantFiled: June 15, 2015Date of Patent: February 27, 2018Assignee: D.E. Shaw Research, LLCInventors: J. P. Grossman, Brian Patrick Towles
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Publication number: 20150365329Abstract: A data communication apparatus includes a router, first and second packet producers, and a penalizer. The router is directly connected to the first and second producers. The penalizer assesses penalties against each producer whenever that producer is serviced. The penalty value depends at least in part on an expected extent to which the first producer requires service. The penalizer then accumulates penalties against each producer.Type: ApplicationFiled: June 15, 2015Publication date: December 17, 2015Inventors: J.P. Grossman, Brian Patrick Towles
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Patent number: 9031241Abstract: An approach to data communication makes use of a protocol for encoding data on a serial link that provides both a run length limiting function and a frame marking function, while minimizing communication overhead over the data bearing portions of the signal, and while limiting latency introduced into the communication. In some examples, a single bit is added as a frame marker in such a way that a single bit frame marker also limits run length.Type: GrantFiled: February 4, 2010Date of Patent: May 12, 2015Assignee: D.E. Shaw Research, LLCInventors: Larry Nociolo, Brian Patrick Towles
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Patent number: 7809006Abstract: An approach to introducing adaptive routing into a communication approach for passing messages between nodes over links between the nodes includes forming virtual channels over the links of the system and defining a deterministic routing function over the virtual channels such that the deterministic routing function is deadlock free. Adaptive routing is then permitted at nodes using the existing virtual channels by introducing a constraint on the available virtual channels used to forward communication that arrives at a node for a particular destination. The constraint on the virtual channels is such that the adaptive system is also deadlock free.Type: GrantFiled: August 12, 2008Date of Patent: October 5, 2010Assignee: D. E. Shaw Research, LLCInventor: Brian Patrick Towles
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Publication number: 20100195835Abstract: An approach to data communication makes use of a protocol for encoding data on a serial link that provides both a run length limiting function and a frame marking function, while minimizing communication overhead over the data bearing portions of the signal, and while limiting latency introduced into the communication. In some examples, a single bit is added as a frame marker in such a way that a single bit frame marker also limits run length.Type: ApplicationFiled: February 4, 2010Publication date: August 5, 2010Applicant: D.E. Shaw Research, LLCInventors: Larry Nociolo, Brian Patrick Towles
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Publication number: 20090046727Abstract: An approach to introducing adaptive routing into a communication approach for passing messages between nodes over links between the nodes includes forming virtual channels over the links of the system and defining a deterministic routing function over the virtual channels such that the deterministic routing function is deadlock free. Adaptive routing is then permitted at nodes using the existing virtual channels by introducing a constraint on the available virtual channels used to forward communication that arrives at a node for a particular destination. The constraint on the virtual channels is such that the adaptive system is also deadlock free.Type: ApplicationFiled: August 12, 2008Publication date: February 19, 2009Applicant: D. E. Shaw Research, LLCInventor: Brian Patrick Towles
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Patent number: 7346049Abstract: A scheduling algorithm is provided that may be implemented in a multi-stage switch requiring less switching elements than known switching architectures in order to increase bandwidth and to retain the non-blocking properties of the constituent switching elements for incoming traffic, including multicast traffic. A scheduling algorithm is also provided for incremental scheduling of connections being added or removed from the switch.Type: GrantFiled: February 19, 2003Date of Patent: March 18, 2008Inventor: Brian Patrick Towles
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Publication number: 20030214944Abstract: A scheduling algorithm is provided that may be implemented in a multi-stage switch requiring less switching elements than known switching architectures in order to increase bandwidth and to retain the non-blocking properties of the constituent switching elements for incoming traffic, including multicast traffic. A scheduling algorithm is also provided for incremental scheduling of connections being added or removed from the switch.Type: ApplicationFiled: February 19, 2003Publication date: November 20, 2003Applicant: Velio Communications, Inc.Inventor: Brian Patrick Towles