Patents by Inventor Brian Robert Folsom
Brian Robert Folsom has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9680742Abstract: A circuit operates to manage transmittal of packets in a network packet processor. The circuit includes a packet descriptor manager (PDM), a packet scheduling engine (PSE), and a packet engines and buffering module (PEB). The PDM generates a metapacket and a descriptor from a command signal, where the command signal identifies a packet to be transmitted by the circuit. The PSE determines an order in which to transmit the packet among a number of packets, where the PSE determines the order based on information indicated in the metapacket. Once the packet is scheduled for transmission, the PEB performs processing operations on the packet to produce a processed packet based on instructions indicated in the descriptor. The PEB then causes the processed packet to be transmitted toward the destination.Type: GrantFiled: February 28, 2014Date of Patent: June 13, 2017Assignee: Cavium, Inc.Inventors: Joseph B. Tompkins, Brian Robert Folsom, Wilson P. Snyder, II, Richard E. Kessler, Edwin Langevin, Andrew J. Jones, Ethan F. Robbins, Krupa Sagar O. S. Mylavarapu, Mahesh Dorai, Nagaraj G. Shirali, Ranjith Kumar V. Hallur
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Patent number: 9559982Abstract: A circuit operates to manage transmittal of packets in a network packet processor. The circuit includes a packet descriptor manager (PDM), a packet scheduling engine (PSE), and a packet engines and buffering module (PEB). The PDM generates a metapacket and a descriptor from a command signal, where the command signal identifies a packet to be transmitted by the circuit. The PSE compares a packet transmission rate associated with the packet against at least one of a peak rate and a committed rate associated with the packet, and determines an order in which to transmit the packet among a number of packets based on the comparison. Once the packet is scheduled for transmission, the PEB performs processing operations on the packet to produce a processed packet based on instructions indicated in the descriptor. The PEB then causes the processed packet to be transmitted toward the destination.Type: GrantFiled: February 28, 2014Date of Patent: January 31, 2017Assignee: Cavium, Inc.Inventors: Brian Robert Folsom, Joseph B. Tompkins, Wilson P. Snyder, II, Richard E. Kessler, Edwin Langevin, Andrew J. Jones, Ethan F. Robbins
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Patent number: 9397938Abstract: A circuit operates to manage transmittal of packets in a network packet processor. The circuit includes a packet descriptor manager (PDM), a packet scheduling engine (PSE), and a packet engines and buffering module (PEB). The PDM generates a metapacket and a descriptor from a command signal, where the command signal identifies a packet to be transmitted by the circuit. The PSE models the packet through a model of the network topology, determining an order in which to transmit the packet among a number of packets based on the modeling. Once the packet is scheduled for transmission, the PEB performs processing operations on the packet to produce a processed packet based on instructions indicated in the descriptor. The PEB then causes the processed packet to be transmitted toward the destination.Type: GrantFiled: February 28, 2014Date of Patent: July 19, 2016Assignee: Cavium, Inc.Inventors: Brian Robert Folsom, Joseph B. Tompkins, Wilson P. Snyder, II, Richard E. Kessler, Edwin Langevin, Andrew J. Jones, Ethan F. Robbins
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Publication number: 20150249604Abstract: A circuit operates to manage transmittal of packets in a network packet processor. The circuit includes a packet descriptor manager (PDM), a packet scheduling engine (PSE), and a packet engines and buffering module (PEB). The PDM generates a metapacket and a descriptor from a command signal, where the command signal identifies a packet to be transmitted by the circuit. The PSE models the packet through a model of the network topology, determining an order in which to transmit the packet among a number of packets based on the modeling. Once the packet is scheduled for transmission, the PEB performs processing operations on the packet to produce a processed packet based on instructions indicated in the descriptor. The PEB then causes the processed packet to be transmitted toward the destination.Type: ApplicationFiled: February 28, 2014Publication date: September 3, 2015Applicant: CAVIUM, INC.Inventors: Brian Robert Folsom, Joseph B. Tompkins, Wilson P. Snyder, II, Richard E. Kessler, Edwin Langevin, Andrew J. Jones, Ethan F. Robbins
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Publication number: 20150249603Abstract: A circuit operates to manage transmittal of packets in a network packet processor. The circuit includes a packet descriptor manager (PDM), a packet scheduling engine (PSE), and a packet engines and buffering module (PEB). The PDM generates a metapacket and a descriptor from a command signal, where the command signal identifies a packet to be transmitted by the circuit. The PSE determines an order in which to transmit the packet among a number of packets, where the PSE determines the order based on information indicated in the metapacket. Once the packet is scheduled for transmission, the PEB performs processing operations on the packet to produce a processed packet based on instructions indicated in the descriptor. The PEB then causes the processed packet to be transmitted toward the destination.Type: ApplicationFiled: February 28, 2014Publication date: September 3, 2015Applicant: Cavium, Inc.Inventors: Joseph B. Tompkins, Brian Robert Folsom, Wilson P. Snyder, II, Richard E. Kessler, Edwin Langevin, Andrew J. Jones, Ethan F. Robbins, Krupa Sagar O.S. Mylavarapu, Mahesh Dorai, Nagaraj G. Shirali, Ranjith Kumar V. Hallur
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Publication number: 20150249620Abstract: A circuit operates to manage transmittal of packets in a network packet processor. The circuit includes a packet descriptor manager (PDM), a packet scheduling engine (PSE), and a packet engines and buffering module (PEB). The PDM generates a metapacket and a descriptor from a command signal, where the command signal identifies a packet to be transmitted by the circuit. The PSE compares a packet transmission rate associated with the packet against at least one of a peak rate and a committed rate associated with the packet, and determines an order in which to transmit the packet among a number of packets based on the comparison. Once the packet is scheduled for transmission, the PEB performs processing operations on the packet to produce a processed packet based on instructions indicated in the descriptor. The PEB then causes the processed packet to be transmitted toward the destination.Type: ApplicationFiled: February 28, 2014Publication date: September 3, 2015Applicant: Cavium, Inc.Inventors: Brian Robert Folsom, Joseph B. Tompkins, Wilson P. Snyder, II, Richard E. Kessler, Edwin Langevin, Andrew J. Jones, Ethan F. Robbins
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Patent number: 7173452Abstract: A re-programmable finite state machine comprising a content-addressable memory (“CAM”) and a read/write memory output array (“OA”). In operation, the CAM receives and periodically latches a status vector, and generates a match vector as a function of the status vector and a set of stored compare vectors. In response, the OA selects for output one of a set of a control vector as a function of the match vector. A state vector portion of the selected control vector is forwarded to the CAM as a portion of the status vector. An output vector portion of the selected control vector controls the operation of external components. Both the set of stored compare vectors and the set of control vectors are fully re-programmable.Type: GrantFiled: September 16, 2002Date of Patent: February 6, 2007Assignee: Emulex Design & Manufacturing CorporationInventor: Brian Robert Folsom
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Publication number: 20040054848Abstract: A re-programmable finite state machine comprising a content-addressable memory (“CAM”) and a read/write memory output array (“OA”). In operation, the CAM receives and periodically latches a status vector, and generates a match vector as a function of the status vector and a set of stored compare vectors. In response, the OA selects for output one of a set of a control vector as a function of the match vector. A state vector portion of the selected control vector is forwarded to the CAM as a portion of the status vector. An output vector portion of the selected control vector controls the operation of external components. Both the set of stored compare vectors and the set of control vectors are fully re-programmable.Type: ApplicationFiled: September 16, 2002Publication date: March 18, 2004Inventor: Brian Robert Folsom