Patents by Inventor Brian S. Morris
Brian S. Morris has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240012759Abstract: A shared memory controller receives a flit from another first shared memory controller over a shared memory link, where the flit includes a node identifier (ID) field and an address of a particular line of the shared memory. The node ID field identifies that the first shared memory controller corresponds to a source of the flit. Further, a second shared memory controller is determined from at least the address field of the flit, where the second shared memory controller is connected to a memory element corresponding to the particular line.Type: ApplicationFiled: September 7, 2023Publication date: January 11, 2024Applicant: Intel CorporationInventors: Debendra Das Sharma, Michelle C. Jen, Brian S. Morris
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Patent number: 11755486Abstract: A shared memory controller receives a flit from another first shared memory controller over a shared memory link, where the flit includes a node identifier (ID) field and an address of a particular line of the shared memory. The node ID field identifies that the first shared memory controller corresponds to a source of the flit. Further, a second shared memory controller is determined from at least the address field of the flit, where the second shared memory controller is connected to a memory element corresponding to the particular line. The flit is forwarded to the second shared memory controller using a shared memory link according to a routing path.Type: GrantFiled: April 21, 2021Date of Patent: September 12, 2023Assignee: Intel CorporationInventors: Debendra Das Sharma, Michelle C. Jen, Brian S. Morris
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Publication number: 20220012189Abstract: A shared memory controller is to service load and store operations received, over data links, from a plurality of independent nodes to provide access to a shared memory resource. Each of the plurality of independent nodes is to be permitted to access a respective portion of the shared memory resource. Interconnect protocol data and memory access protocol data are sent on the data links and transitions between the interconnect protocol data and memory access protocol data can be defined and identified.Type: ApplicationFiled: September 25, 2021Publication date: January 13, 2022Applicant: Intel CorporationInventors: Debendra Das Sharma, Robert G. Blankenship, Suresh S. Chittor, Kenneth C. Creta, Balint Fleischer, Michelle C. Jen, Mohan J. Kumar, Brian S. Morris
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Publication number: 20210303482Abstract: A shared memory controller is to service load and store operations received, over data links, from a plurality of independent nodes to provide access to a shared memory resource. Each of the plurality of independent nodes is to be permitted to access a respective portion of the shared memory resource. Interconnect protocol data and memory access protocol data are sent on the data links and transitions between the interconnect protocol data and memory access protocol data can be defined and identified.Type: ApplicationFiled: February 8, 2021Publication date: September 30, 2021Applicant: Intel CorporationInventors: Debendra Das Sharma, Robert G. Blankenship, Suresh S. Chittor, Kenneth C. Creta, Balint Fleischer, Michelle C. Jen, Mohan J. Kumar, Brian S. Morris
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Patent number: 11113196Abstract: A shared memory controller receives a flit from another first shared memory controller over a shared memory link, where the flit includes a node identifier (ID) field and an address of a particular line of the shared memory. The node ID field identifies that the first shared memory controller corresponds to a source of the flit. Further, a second shared memory controller is determined from at least the address field of the flit, where the second shared memory controller is connected to a memory element corresponding to the particular line. The flit is forwarded to the second shared memory controller using a shared memory link according to a routing path.Type: GrantFiled: September 24, 2018Date of Patent: September 7, 2021Assignee: Intel CorporationInventors: Debendra Das Sharma, Michelle C. Jen, Brian S. Morris
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Publication number: 20210263993Abstract: Methods and apparatuses relating to performing vector multiplication are described. Hardware accelerators to perform vector multiplication are also described.Type: ApplicationFiled: September 27, 2018Publication date: August 26, 2021Inventors: Maciej URBANSKI, Brian J. HICKMANN, Michael ROTZIN, Krishnakumar NAIR, Andrew YANG, Brian S. MORRIS, Dennis BRADFORD
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Publication number: 20210240623Abstract: A shared memory controller receives a flit from another first shared memory controller over a shared memory link, where the flit includes a node identifier (ID) field and an address of a particular line of the shared memory. The node ID field identifies that the first shared memory controller corresponds to a source of the flit. Further, a second shared memory controller is determined from at least the address field of the flit, where the second shared memory controller is connected to a memory element corresponding to the particular line.Type: ApplicationFiled: April 21, 2021Publication date: August 5, 2021Applicant: Intel CorporationInventors: Debendra Das Sharma, Michelle C. Jen, Brian S. Morris
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Patent number: 10915468Abstract: A shared memory controller is to service load and store operations received, over data links, from a plurality of independent nodes to provide access to a shared memory resource. Each of the plurality of independent nodes is to be permitted to access a respective portion of the shared memory resource. Interconnect protocol data and memory access protocol data are sent on the data links and transitions between the interconnect protocol data and memory access protocol data can be defined and identified.Type: GrantFiled: December 26, 2013Date of Patent: February 9, 2021Assignee: Intel CorporationInventors: Debendra Das Sharma, Robert G. Blankenship, Suresh S. Chittor, Kenneth C. Creta, Balint Fleischer, Michelle C. Jen, Mohan J. Kumar, Brian S. Morris
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Patent number: 10671740Abstract: A processor implementing techniques for supporting configurable security levels for memory address ranges is disclosed. In one embodiment, the processor includes a processing core a memory controller, operatively coupled to the processing core, to access data in an off-chip memory and a memory encryption engine (MEE) operatively coupled to the memory controller. The MEE is to responsive to detecting a memory access operation with respect to a memory location identified by a memory address within a memory address range associated with the off-chip memory, identify a security level indicator associated with the memory location based on a value stored on a security range register. The MEE is further to access at least a portion of a data item associated with the memory address range of the off-chip memory in view of the security level indicator.Type: GrantFiled: April 5, 2018Date of Patent: June 2, 2020Assignee: Intel CorporationInventors: Binata Bhattacharyya, Raghunandan Makaram, Amy L. Santoni, George Z. Chrysos, Simon P. Johnson, Brian S. Morris, Francis X. McKeen
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Patent number: 10579464Abstract: Provided are an apparatus and method to store data from a cache line at locations having errors in a sparing directory. In response to a write operation having write data for locations in one of the cache lines, the write data for a location in the cache line having an error is written to an entry in a sparing directory including an address of the cache line.Type: GrantFiled: March 5, 2018Date of Patent: March 3, 2020Assignee: INTEL CORPORATIONInventors: Debaleena Das, Rajat Agarwal, Brian S. Morris
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Patent number: 10360096Abstract: Data is sent from a memory buffer device to a host device over a link. An error in the data is determined. A read response cancellation signal is sent to the host device to indicate the error to the host device, where the read response cancellation signal is to be sent subsequent to the data being sent from the memory buffer device to the host device.Type: GrantFiled: March 17, 2017Date of Patent: July 23, 2019Assignee: Intel CorporationInventors: Brian S. Morris, Bill Nale, Robert G. Blankenship, Eric L. Hendrickson
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Publication number: 20190108124Abstract: A shared memory controller receives a flit from another first shared memory controller over a shared memory link, where the flit includes a node identifier (ID) field and an address of a particular line of the shared memory. The node ID field identifies that the first shared memory controller corresponds to a source of the flit. Further, a second shared memory controller is determined from at least the address field of the flit, where the second shared memory controller is connected to a memory element corresponding to the particular line.Type: ApplicationFiled: September 24, 2018Publication date: April 11, 2019Applicant: Intel CorporationInventors: Debendra Das Sharma, Michelle C. Jen, Brian S. Morris
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Patent number: 10198379Abstract: A sequence of read returns are to be sent to a host device over a transactional buffered memory interface, where the sequence includes at least a first read return to a first read request and a second read return to a second read request. A tracker identifier of the second read return is encoded in the first read return and the first read return is sent with the tracker identifier of the second read return to the host device. The second read return is sent to the host device after the first read return is sent.Type: GrantFiled: August 4, 2017Date of Patent: February 5, 2019Assignee: Intel CorporationInventors: Brian S. Morris, Bill Nale, Robert G. Blankenship, Jeffrey C. Swanson
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Patent number: 10163508Abstract: Methods and apparatus related to supporting both DDR (Double Data Rate) and NVM (Non-Volatile Memory) DIMM (Dual Inline Memory Module) on the same memory slot are described. In one embodiment, a DIMM comprises volatile memory and non-volatile memory, and data is communicated with the volatile memory and the non-volatile memory via a single memory slot. Other embodiments are also disclosed and claimed.Type: GrantFiled: February 26, 2016Date of Patent: December 25, 2018Assignee: Intel CorporationInventors: Woojong Han, Mohamed Arafa, Brian S. Morris, Mani Prakash, James K. Pickett, John K. Grooms, Bruce Querbach, Edward L Payton, Dong Wang
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Publication number: 20180365438Abstract: A processor implementing techniques for supporting configurable security levels for memory address ranges is disclosed. In one embodiment, the processor includes a processing core a memory controller, operatively coupled to the processing core, to access data in an off-chip memory and a memory encryption engine (MEE) operatively coupled to the memory controller. The MEE is to responsive to detecting a memory access operation with respect to a memory location identified by a memory address within a memory address range associated with the off-chip memory, identify a security level indicator associated with the memory location based on a value stored on a security range register. The MEE is further to access at least a portion of a data item associated with the memory address range of the off-chip memory in view of the security level indicator.Type: ApplicationFiled: April 5, 2018Publication date: December 20, 2018Inventors: Binata Bhattacharyya, Raghunandan Makaram, Amy L. Santoni, George Z. Chrysos, Simon P. Johnson, Brian S. Morris, Francis X. McKeen
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Patent number: 10102886Abstract: Examples are disclosed for probabilistic dynamic random access memory (DRAM) row repair. In some examples, using a row hammer limit for DRAM and a maximum activation rate for the DRAM a probabilistic row hammer detection value may be determined. The probabilistic row hammer detection value may then be used such that a probability is acceptably low that a given activation to an aggressor row of the DRAM causes the row hammer limit to be exceeded before a scheduled row refresh is performed on one or more victim rows associated with the aggressor row. Other examples are described and claimed.Type: GrantFiled: September 19, 2016Date of Patent: October 16, 2018Assignee: INTEL CORPORATIONInventors: John H. Crawford, Brian S. Morris, Sreenivas Mandava, Raj K. Ramanujan
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Patent number: 10061719Abstract: A plurality of completed writes to memory are identified corresponding to a plurality of write requests from a host device received over a buffered memory interface. A completion packet is sent to the host device that includes a plurality of write completions to correspond to the plurality of completed writes.Type: GrantFiled: December 25, 2014Date of Patent: August 28, 2018Assignee: Intel CorporationInventors: Brian S. Morris, Jeffrey C. Swanson, Bill Nale, Robert G. Blankenship, Jeff Willey, Eric L. Hendrickson
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Patent number: 10042562Abstract: Provided are an apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device having a 2n cache size. A request is to a target address having n bits directed to the second level memory device. A determination is made whether a target index, comprising m bits of the n bits of the target address, is within an index set of the first level memory device. A determination is made of a modified target index in the index set of the first level memory device having at least one index bit that differs from a corresponding at least one index bit in the target index. The request is processed with respect to data in a cache line at the modified target index in the first level memory device.Type: GrantFiled: August 23, 2017Date of Patent: August 7, 2018Assignee: Intel CorporationInventors: Vedaraman Geetha, Henk G. Neefs, Brian S. Morris, Sreenivas Mandava, Massimo Sutera
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Patent number: 10031861Abstract: A server, processing device and/or processor includes a processing core and a memory controller, operatively coupled to the processing core, to access data in an off-chip memory. A memory encryption engine (MEE) may be operatively coupled to the memory controller and the off-chip memory. The MEE may store non-MEE metadata bits within a modified version line corresponding to ones of a plurality of data lines stored in a protected region of the off-chip memory, compute an embedded message authentication code (eMAC) using the modified version line, and detect an attempt to modify one of the non-MEE metadata bits by using the eMAC within a MEE tree walk to authenticate access to the plurality of data lines. The non-MEE metadata bits may store coherence bits that track changes to a cache line in a remote socket, poison bits that track error containment within the data lines, and possibly other metadata bits.Type: GrantFiled: September 25, 2015Date of Patent: July 24, 2018Assignee: Intel CorporationInventors: Siddhartha Chhabra, Binata Bhattacharyya, Raghunandan Makaram, Brian S. Morris
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Publication number: 20180196709Abstract: Provided are an apparatus and method to store data from a cache line at locations having errors in a sparing directory. In response to a write operation having write data for locations in one of the cache lines, the write data for a location in the cache line having an error is written to an entry in a sparing directory including an address of the cache line.Type: ApplicationFiled: March 5, 2018Publication date: July 12, 2018Inventors: Debaleena DAS, Rajat AGARWAL, Brian S. MORRIS