Patents by Inventor Brian Slechta

Brian Slechta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220407803
    Abstract: Technologies for quality of service based throttling in a fabric architecture include a network node of a plurality of network nodes interconnected across the fabric architecture via an interconnect fabric. The network node includes a host fabric interface (HFI) configured to facilitate the transmission of data to/from the network node, monitor quality of service levels of resources of the network node used to process and transmit the data, and detect a throttling condition based on a result of the monitored quality of service levels. The HFI is further configured to generate and transmit a throttling message to one or more of the interconnected network nodes in response to having detected a throttling condition. The HFI is additionally configured to receive a throttling message from another of the network nodes and perform a throttling action on one or more of the resources based on the received throttling message. Other embodiments are described herein.
    Type: Application
    Filed: May 17, 2022
    Publication date: December 22, 2022
    Applicant: Intel Corporation
    Inventors: Francesc Guim Bernat, Karthik Kumar, Thomas Willhalm, Raj Ramanujan, Brian Slechta
  • Patent number: 11343177
    Abstract: Technologies for quality of service based throttling in a fabric architecture include a network node of a plurality of network nodes interconnected across the fabric architecture via an interconnect fabric. The network node includes a host fabric interface (HFI) configured to facilitate the transmission of data to/from the network node, monitor quality of service levels of resources of the network node used to process and transmit the data, and detect a throttling condition based on a result of the monitored quality of service levels. The HFI is further configured to generate and transmit a throttling message to one or more of the interconnected network nodes in response to having detected a throttling condition. The HFI is additionally configured to receive a throttling message from another of the network nodes and perform a throttling action on one or more of the resources based on the received throttling message. Other embodiments are described herein.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: May 24, 2022
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Karthik Kumar, Thomas Willhalm, Raj Ramanujan, Brian Slechta
  • Publication number: 20210051096
    Abstract: Technologies for quality of service based throttling in a fabric architecture include a network node of a plurality of network nodes interconnected across the fabric architecture via an interconnect fabric. The network node includes a host fabric interface (HFI) configured to facilitate the transmission of data to/from the network node, monitor quality of service levels of resources of the network node used to process and transmit the data, and detect a throttling condition based on a result of the monitored quality of service levels. The HFI is further configured to generate and transmit a throttling message to one or more of the interconnected network nodes in response to having detected a throttling condition. The HFI is additionally configured to receive a throttling message from another of the network nodes and perform a throttling action on one or more of the resources based on the received throttling message. Other embodiments are described herein.
    Type: Application
    Filed: October 30, 2020
    Publication date: February 18, 2021
    Inventors: Francesc Guim Bernat, Karthik Kumar, Thomas Willhalm, Raj Ramanujan, Brian Slechta
  • Patent number: 9983996
    Abstract: Technologies for managing cache memory of a processor in a distributed shared memory system includes managing a distance value and an age value associated with each cache line of the cache memory. The distance value is indicative of a distance of a memory resource, relative to the processor, from which data stored in the corresponding chance line originates. The age value is based on the distance value and the number of times for which the corresponding cache line has been considered for eviction since a previous eviction of the corresponding cache line. Initially, the age value is set to the distance value. Additionally, every time a cache line is accessed, the age value associated with the accessed cache line is reset to the corresponding distance value. During a cache eviction operation, the cache line for eviction is selected based on the age value associated with each cache line.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: May 29, 2018
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Karthik Kumar, Thomas Willhalm, Brian Slechta
  • Publication number: 20170168942
    Abstract: Technologies for managing cache memory of a processor in a distributed shared memory system includes managing a distance value and an age value associated with each cache line of the cache memory. The distance value is indicative of a distance of a memory resource, relative to the processor, from which data stored in the corresponding chance line originates. The age value is based on the distance value and the number of times for which the corresponding cache line has been considered for eviction since a previous eviction of the corresponding cache line. Initially, the age value is set to the distance value. Additionally, every time a cache line is accessed, the age value associated with the accessed cache line is reset to the corresponding distance value. During a cache eviction operation, the cache line for eviction is selected based on the age value associated with each cache line.
    Type: Application
    Filed: December 10, 2015
    Publication date: June 15, 2017
    Inventors: Francesc Guim Bernat, Karthik Kumar, Thomas Willhalm, Brian Slechta