Abstract: A weighted round-robin arbitrator for a plurality of data queue includes an arbitration table comprising a plurality of entries. Each entry represents a time slot for the transmission of one data packet from a selected one of the plurality of data queues. There is one arbitration logic circuit for each of the plurality of entries in the arbitration table. Each arbitration logic circuit includes a first multiplexer receiving an output from a first table entry and an output from a second table entry in the arbitration table. A second multiplexer receives empty flags from each of the data queues, the flags indicating that there is no data to the sent from that queue.

Abstract: A bridge controller controls the data flow to/from a USB bus to/from an ATA/ATAPI drive, such as an ATA hard drive or ATAPI CD or DVD drive. The bridge controller has a state machine which receives the CBW in a background mode in real time as the packet is being transferred to the bridge controller. The state machine uses the CBW to set up the data transfer. The bridge controller also has a programmable processor which is coupled to the CBW once it is received in a buffer memory. The programmable processor makes changes in the set up of the receiving device for the transfer, if needed, and initiates the data transfer.

Abstract: Apparatus and method for microcontroller debugging. A preferred embodiment microcontroller integrated circuit comprises debug circuitry on the integrated circuit. The debug circuitry is capable of breaking normal instruction execution based on an address breakpoint, a stack pointer breakpoint, or a single step breakpoint. Upon detection of a valid breakpoint, the debug circuitry substitutes a jump to a debug program instruction in place of the next normal application program instruction. The debug program then may provide microcontroller status to a developer, allowing the developer to debug the application program. Upon completion of the debug program, control of the microcontroller is returned to the application program at the point of interruption.

Abstract: A controller that supports both aligned and unaligned PIO data transfers associated with ATAPI devices in a fashion that reduces command overhead to improve ATAPI device system performance. A 32-bit wide sector FIFO, implemented with a 32-bit single port RAM using read and write pointer control logic, is used to store packet data transmitted to and received from the other data bus (i.e. USB). The 32-bit single port RAM functions as a FIFO to allow both the USB side and the ATAPI side to simultaneously access the sector FIFO.

Abstract: A method and system are provided to implement firmware encryption and decryption for firmware that must be downloaded from an external on-board ROM, for example, into the RAM of a controller IC. Encrypted firmware is provided using a combination of hardware, firmware and a unique on-chip serial number (die ID). The hardware and associated firmware are provided in a manner that does not require public and/or private keys. The encrypted firmware image is different for each end product such that a unique and unknown encryption key is generated for each end product.

Abstract: A controller that supports both aligned and unaligned PIO data transfers associated with ATAPI devices in a fashion that reduces command overhead to improve ATAPI device system performance. A 32-bit wide sector FIFO, implemented with a 32-bit single port RAM using read and write pointer control logic, is used to store packet data transmitted to and received from the other data bus (i.e. USB). The 32-bit single port RAM functions as a FIFO to allow both the USB side and the ATAPI side to simultaneously access the sector FIFO.

Abstract: As communications busses become more generic, the handshaking that occurs to provide communications become more complicated. The constant checking of signal lines for a stable and debounced signal can consume a considerable amount of overhead and greatly increase the complexity of the design of the hardware. An independent debouncing circuit 505 and 600 can be used to detect the presence of a stable and debounced signal and notify an interface engine 320. A state machine 800 executing in the interface engine 320 uses the stable and debounced signals to control operation of a peripheral connected to the bus by monitoring signals passed on the bus.

Abstract: A microprocessor interrupt controller capable of receiving a plurality of interrupt requests organized in a plurality of groups, at least one of the groups including a plurality of interrupt requests, and providing the interrupts requests to a microprocessor. The controller includes a plurality of storage units corresponding to the plurality of groups and capable of storing one or more of the interrupt requests, by group, and providing the interrupt requests so stored as outputs, on a first in first out basis. At least one write arbiter unit is also included, associated with the storage unit for the at least one of the groups including a plurality of interrupt requests, for providing simultaneously pending interrupt requests of the at least one of the groups to the associated storage unit on a priority basis.

Abstract: Apparatus and method for microcontroller debugging. A preferred embodiment microcontroller integrated circuit comprises debug circuitry on the integrated circuit. The debug circuitry is capable of breaking normal instruction execution based on an address breakpoint, a stack pointer breakpoint, or a single step breakpoint. Upon detection of a valid breakpoint, the debug circuitry substitutes a jump to a debug program instruction in place of the next normal application program instruction. The debug program then may provide microcontroller status to a developer, allowing the developer to debug the application program. Upon completion of the debug program, control of the microcontroller is returned to the application program at the point of interruption.

Abstract: The invention comprises a method and system for testing memory in an interface system 10 coupling a parallel host bus 30 to a serial bus 20. The system comprises a random access memory 70 having a plurality of memory locations for temporarily storing data received from either the parallel host bus 30 or the IEEE 1394 serial bus 20, the random access memory 70 being logically divided into a transmit memory portion and a receive memory portion. The interface also comprises a transmission control unit 40 operable to control transmission of data from the parallel host bus 30 to the IEEE 1394 serial bus 20. The transmission control unit 40 is further operable to access the transmit memory portion of the random access memory 70. The interface also comprises a reception control unit 50 operable to control reception of data by the parallel bus 30 from the serial bus 20. The receive control unit 50 is further operable to access the receive memory portion of the random access memory 70.