Patents by Inventor Brian V. Belmont

Brian V. Belmont has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120166243
    Abstract: Methods and apparatuses for scheduling a task using field data are provided. Field data can be used to more accurately predict and continually adjust the estimated amount of time to complete a work order when scheduling resources.
    Type: Application
    Filed: December 27, 2010
    Publication date: June 28, 2012
    Inventors: Brian V. Belmont, Jurgen Hatheier, Michael P. Gordish, Kishor G. Yadav, Steven Cardenas
  • Publication number: 20120110512
    Abstract: A integrated content guide for multiple sources is provided with hyper-text type links to allow for the selection of various programs. The hyper-text links are provided for a transmitted and then stored digital bit stream. This allows for the embedding within the content guide what could be additional commercial information. The embedding may also be as to additional information for other related television or radio shows or the like. Information can be additional television shows, related information or activities on on-line services or automatic telephone ordering of products or services being displayed.
    Type: Application
    Filed: January 3, 2012
    Publication date: May 3, 2012
    Inventors: John P. Stautner, Richard J. Lawson, Brian V. Belmont
  • Patent number: 8166325
    Abstract: A computing system is described that includes a main system bus that remains active while said computing system operates within a non main CPU/OS based operational state. The computing system also includes a controller that operates functional tasks while the computing system is within the non main CPU/OS based operational state. The computing system also includes an I/O unit coupled to the main system bus that remains active while the computing system operates within the non main CPU/OS based operational state.
    Type: Grant
    Filed: September 22, 2008
    Date of Patent: April 24, 2012
    Assignee: Intel Corporation
    Inventors: James P. Kardach, Brian V. Belmont, Muthu K. Kumar, Riley W. Jackson, Gunner Danneels, Richard A. Forand, Vivek Gupta, Jeffrey L. Huckins, Kristoffer D. Flemming, Uma M. Gadamsetty
  • Patent number: 8156351
    Abstract: An embodiment of the present invention is a technique to dynamically swap processor cores. A first core has a first instruction set. The first core executes a program at a first performance level. The first core stops executing the program when a triggering event occurs. A second core has a second instruction set compatible with the first instruction set and has a second performance level different than the first performance level. The second core is in a power down state when the first core is executing the program. A circuit powers up the second core after the first core stops executing the program such that the second core continues executing the program at the second performance level.
    Type: Grant
    Filed: December 2, 2008
    Date of Patent: April 10, 2012
    Assignee: Intel Corporation
    Inventors: Brian V. Belmont, Animesh Mishra, James P. Kardach
  • Patent number: 8108797
    Abstract: A integrated content guide for multiple sources is provided with hyper-text type links to allow for the selection of various programs. The hyper-text links are provided for a transmitted and then stored digital bit stream. This allows for the embedding within the content guide what could be additional commercial information. The embedding may also be as to additional information for other related television or radio shows or the like. Information can be additional television shows, related information or activities on on-line services or automatic telephone ordering of products or services being displayed.
    Type: Grant
    Filed: February 4, 2010
    Date of Patent: January 31, 2012
    Assignee: Exaflop LLC
    Inventors: John P. Stautner, Richard J. Lawson, Brian V. Belmont
  • Publication number: 20100138487
    Abstract: A integrated content guide for multiple sources is provided with hyper-text type links to allow for the selection of various programs. The hyper-text links are provided for a transmitted and then stored digital bit stream. This allows for the embedding within the content guide what could be additional commercial information. The embedding may also be as to additional information for other related television or radio shows or the like. Information can be additional television shows, related information or activities on on-line services or automatic telephone ordering of products or services being displayed.
    Type: Application
    Filed: February 4, 2010
    Publication date: June 3, 2010
    Inventors: John P. Stautner, Richard J. Lawson, Brian V. Belmont
  • Patent number: 7694235
    Abstract: A integrated content guide for multiple sources is provided with hyper-text type links to allow for the selection of various programs. The hyper-text links are provided for a transmitted and then stored digital bit stream. This allows for the embedding within the content guide what could be additional commercial information. The embedding may also be as to additional information for other related television or radio shows or the like. Information can be additional television shows, related information or activities on on-line services or automatic telephone ordering of products or services being displayed.
    Type: Grant
    Filed: July 28, 2008
    Date of Patent: April 6, 2010
    Assignee: Exaflop LLC
    Inventors: John P. Stautner, Richard J. Lawson, Brian V. Belmont
  • Publication number: 20090083554
    Abstract: An embodiment of the present invention is a technique to dynamically swap processor cores. A first core has a first instruction set. The first core executes a program at a first performance level. The first core stops executing the program when a triggering event occurs. A second core has a second instruction set compatible with the first instruction set and has a second performance level different than the first performance level. The second core is in a power down state when the first core is executing the program. A circuit powers up the second core after the first core stops executing the program such that the second core continues executing the program at the second performance level.
    Type: Application
    Filed: December 2, 2008
    Publication date: March 26, 2009
    Applicant: INTEL CORPORATION
    Inventors: Brian V. Belmont, Animesh Mishra, James P. Kardach
  • Publication number: 20090025033
    Abstract: A integrated content guide for multiple sources is provided with hyper-text type links to allow for the selection of various programs. The hyper-text links are provided for a transmitted and then stored digital bit stream. This allows for the embedding within the content guide what could be additional commercial information. The embedding may also be as to additional information for other related television or radio shows or the like. Information can be additional television shows, related information or activities on on-line services or automatic telephone ordering of products or services being displayed.
    Type: Application
    Filed: July 28, 2008
    Publication date: January 22, 2009
    Inventors: JOHN P. STAUTNER, Richard J. Lawson, Brian V. Belmont
  • Publication number: 20090019185
    Abstract: A computing system is described that includes a main system bus that remains active while said computing system operates within a non main CPU/OS based operational state. The computing system also includes a controller that operates functional tasks while the computing system is within the non main CPU/OS based operational state. The computing system also includes an I/O unit coupled to the main system bus that remains active while the computing system operates within the non main CPU/OS based operational state.
    Type: Application
    Filed: September 22, 2008
    Publication date: January 15, 2009
    Inventors: James P. Kardach, Brian V. Belmont, Muthu K. Kumar, Riley W. Jackson, Gunner Danneels, Richard A. Forand, Vivek Gupta, Jeffrey L. Huckins, Kristoffer D. Flemming, Uma M. Gadamsetty
  • Patent number: 7461275
    Abstract: An embodiment of the present invention is a technique to dynamically swap processor cores. A first core has a first instruction set. The first core executes a program at a first performance level. The first core stops executing the program when a triggering event occurs. A second core has a second instruction set compatible with the first instruction set and has a second performance level different than the first performance level. The second core is in a power down state when the first core is executing the program. A circuit powers up the second core after the first core stops executing the program such that the second core continues executing the program at the second performance level.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: December 2, 2008
    Assignee: Intel Corporation
    Inventors: Brian V. Belmont, Animesh Mishra, James P. Kardach
  • Patent number: 7428650
    Abstract: A computing system is described that includes a main system bus that remains active while said computing system operates within a non main CPU/OS based operational state. The computing system also includes a controller that operates functional tasks while the computing system is within the non main CPU/OS based operational state. The computing system also includes an I/O unit coupled to the main system bus that remains active while the computing system operates within the non main CPU/OS based operational state.
    Type: Grant
    Filed: May 15, 2006
    Date of Patent: September 23, 2008
    Assignee: Intel Corporation
    Inventors: James P. Kardach, Brian V. Belmont, Muthu K. Kumar, Riley W. Jackson, Gunner Danneels, Richard A. Forand, Vivek Gupta, Jeffrey L. Huckins, Kristoffer D. Flemming, Uma M. Gadamsetty
  • Patent number: 7421597
    Abstract: A method is described that involves operating a computing system within a normal on state and transitioning from the normal on state to a main CPU/OS based state. In the main CPU/OS based state one or more components of the computing system are inactivated so as to cause the computing system to consume less power in the main CPU/OS based state than in the normal on state. The computing system is able to execute software application routines on a main CPU and a main OS of the computing system while in the main CPU/OS based state.
    Type: Grant
    Filed: October 28, 2005
    Date of Patent: September 2, 2008
    Assignee: Intel Corporation
    Inventors: James P. Kardach, Jeffrey L. Huckins, Kristoffer D. Fleming, Uma M. Gadamsetty, Vivek Gupta, Brian V. Belmont, Muthu K. Kumar, Riley W. Jackson, Gunner Danneels, Richard A. Forand
  • Patent number: 7418672
    Abstract: A integrated content guide for multiple sources is provided with hyper-text type links to allow for the selection of various programs. The hyper-text links are provided for a transmitted and then stored digital bit stream. This allows for the embedding within the content guide what could be additional commercial information. The embedding may also be as to additional information for other related television or radio shows or the like. Information can be additional television shows, related information or activities on on-line services or automatic telephone ordering of products or services being displayed.
    Type: Grant
    Filed: July 28, 2003
    Date of Patent: August 26, 2008
    Inventors: John P. Stautner, Richard J. Lawson, Brian V. Belmont
  • Patent number: 7406610
    Abstract: A method is described that involves operating a computing system within a normal on state and transitioning from the normal on state to a main CPU/OS based state. In the main CPU/OS based state one or more components of the computing system are inactivated so as to cause the computing system to consume less power in the main CPU/OS based state than in the normal on state. The computing system is able to execute software application routines on a main CPU and a main OS of the computing system while in the main CPU/OS based state.
    Type: Grant
    Filed: October 28, 2005
    Date of Patent: July 29, 2008
    Assignee: Intel Corporation
    Inventors: James P. Kardach, Jeffrey L. Huckins, Kristoffer D. Fleming, Uma M. Gadamsetty, Vivek Gupta, Brian V. Belmont, Muthu K. Kumar, Riley W. Jackson, Gunner Danneels, Richard A. Forand
  • Patent number: 7263331
    Abstract: A method and apparatus for a user to interface with a mobile computing device is disclosed. In one embodiment, a method comprises sharing a Bluetooth communications module between a primary processor system and a secondary processor system.
    Type: Grant
    Filed: September 15, 2003
    Date of Patent: August 28, 2007
    Assignee: Intel Corporation
    Inventors: Vivek G. Gupta, James Kardach, Brian V. Belmont, Muthu K. Kumar
  • Patent number: 7114090
    Abstract: A method is described that involves operating a computing system within a normal on state and transitioning from the normal on state to a main CPU/OS based state. In the main CPU/OS based state one or more components of the computing system are inactivated so as to cause the computing system to consume less power in the main CPU/OS based state than in the normal on state. The computing system is able to execute software application routines on a main CPU and a main OS of the computing system while in the main CPU/OS based state.
    Type: Grant
    Filed: February 14, 2003
    Date of Patent: September 26, 2006
    Assignee: Intel Corporation
    Inventors: James P. Kardach, Jeffrey L. Huckins, Kristoffer D. Fleming, Uma M. Gadamsetty, Vivek Gupta, Brian V. Belmont, Muthu K. Kumar, Riley W. Jackson, Gunner Danneels, Richard A. Forand
  • Patent number: 7080271
    Abstract: A computing system is described that includes an I/O unit interface that is deactivated while said computing system operates within a non main CPU/OS based operational state. The computing system also includes a controller that operates functional tasks while the computing system is within the non main CPU/OS based operational state. The computing system also includes an I/O unit that is coupled to both the I/O unit interface and the controller.
    Type: Grant
    Filed: February 14, 2003
    Date of Patent: July 18, 2006
    Assignee: Intel Corporation
    Inventors: James P. Kardach, Brian V. Belmont, Muthu K. Kumar, Riley W. Jackson, Gunner Danneels, Richard A. Forand, Vivek Gupta, Jeffrey L. Huckins, Kristoffer D. Flemming, Uma M. Gadamsetty
  • Publication number: 20040162922
    Abstract: A computing system is described that includes an I/O unit interface that is deactivated while said computing system operates within a non main CPU/OS based operational state. The computing system also includes a controller that operates functional tasks while the computing system is within the non main CPU/OS based operational state. The computing system also includes an 110 unit that is coupled to both the I/O unit interface and the controller.
    Type: Application
    Filed: February 14, 2003
    Publication date: August 19, 2004
    Inventors: James P. Kardach, Brian V. Belmont, Muthu K. Kumar, Riley W. Jackson, Gunner Danneels, Richard A. Forand, Vivek Gupta, Jeffrey L. Huckins, Kristoffer D. Flemming, Uma M. Gadamsetty
  • Publication number: 20040163005
    Abstract: A method is described that involves operating a computing system within a normal on state and transitioning from the normal on state to a main CPU/OS based state. In the main CPU/OS based state one or more components of the computing system are inactivated so as to cause the computing system to consume less power in the main CPU/OS based state than in the normal on state. The computing system is able to execute software application routines on a main CPU and a main OS of the computing system while in the main CPU/OS based state.
    Type: Application
    Filed: February 14, 2003
    Publication date: August 19, 2004
    Inventors: James P. Kardach, Jeffrey L. Huckins, Kristoffer D. Fleming, Uma M. Gadamsetty, Vivek Gupta, Brian V. Belmont, Muthu K. Kumar, Riley W. Jackson, Gunner Danneels, Richard A. Forand