Abstract: A phase delay arrangement for connecting high speed digital ICs, wherein a substantial majority of delay is provided via added passive delay elements. The phase synchronization delay arrangement (circuit connection, system and method) adds delay to the signal propagation path between a driving circuit 110 and receiving circuit 130, in order to match signal propagation between a transmitting/receiving circuit pair. Such phase synchronization delay arrangement is provided substantially by added passive components or devices, e.g., added signal line length, inductors, capacitors, which provide a majority or mainstay of the delay, but can further include single ones of flow-through latches, drivers, and programmable delay lines.

Abstract: A system and circuit for pin fault testing is disclosed. The system includes an external tester and a circuit designed to be tested. The external tester is coupled to pins of the circuit and is configured to enter test data into the circuit. The external tester is also configured to receive continuity data from the circuit and to determine pin faults from a comparison of the test data to the continuity data. The circuit includes a plurality scan cells which are coupled in a chain fashion. When testing input pins, the external tester places a test pattern onto the input pins, stores a continuity pattern into the scan cells that are electro-mechanically coupled to the input pins, serially scans the continuity pattern out of the circuit, and compares the continuity pattern to the test pattern. When testing the output pins, the external tester serially scans a test pattern into the scan cells coupled to the output pins and compares the continuity pattern generated on the output pins to the test pattern.

Abstract: A coherent copyback protocol for a multi-level cache memory system prevents more than one modification from existing in multiple locations and saves access time and data bandwidth. The protocol includes the Latest state. A line in the Latest state has the latest copy of modified data. Additionally, all corresponding lines in any higher cache(s) are marked as invalid and all corresponding lines in any lower level cache(s) are marked as modified.