Patents by Inventor Brian Warwick

Brian Warwick has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240196411
    Abstract: A terminal device in a wireless telecommunication system which transmits a master information block and a first and a second system information block the first and second system information block comprising first and second scheduling information relating to the timing of at least one additional block of system information. The terminal device configured to receive the master information block of system information that comprises a marker instructing the terminal device to ignore the first scheduling information and process only the second scheduling information.
    Type: Application
    Filed: February 21, 2024
    Publication date: June 13, 2024
    Applicant: Sony Group Corporation
    Inventors: Brian Alexander MARTIN, Martin Warwick BEALE
  • Patent number: 11968751
    Abstract: A base station for transmitting system related information in a mobile telecommunications network. The base station is configured to transmit system information for the cell provided by the base station and to broadcast a version synchronisation signal, wherein the version synchronisation signal provides version information regarding the current version of the system information for the cell.
    Type: Grant
    Filed: March 9, 2023
    Date of Patent: April 23, 2024
    Assignees: SONY GROUP CORPORATION, SONY MOBILE COMMUNICATIONS INC.
    Inventors: Shin Horng Wong, Martin Warwick Beale, Brian Alexander Martin, Basuki Priyanto, Nafiseh Mazloum
  • Patent number: 11950243
    Abstract: A terminal device in a wireless telecommunication system which transmits a master information block and a first and a second system information block the first and second system information block comprising first and second scheduling information relating to the timing of at least one additional block of system information. The terminal device configured to receive the master information block of system information that comprises a marker instructing the terminal device to ignore the first scheduling information and process only the second scheduling information.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: April 2, 2024
    Assignee: Sony Corporation
    Inventors: Brian Alexander Martin, Martin Warwick Beale
  • Patent number: 11924913
    Abstract: An apparatus comprising circuitry configured to generate a user equipment identifier which is unique on Anchor cell level or which is unique in RAN notified area level.
    Type: Grant
    Filed: March 14, 2022
    Date of Patent: March 5, 2024
    Assignee: Sony Group Corporation
    Inventors: Brian Alexander Martin, Shin Horng Wong, Martin Warwick Beale, Yuxin Wei, Vivek Sharma, Shinichiro Tsuda, Hideji Wakabayashi, Samuel Asangbeng Atungsiri
  • Patent number: 11917539
    Abstract: A terminal device for use with a wireless telecommunications system, the terminal device configured to attempt to receive or to transmit a first signal during one or more of a plurality of predetermined time periods in response to determining that one or more second signals indicating, respectively, that the one or more of the plurality of predetermined time periods should be used for the attempted reception or transmission of a first signal have been received by the transceiver; determine a characteristic associated with the one or more second signals; and to control the transceiver to receive a third signal from the infrastructure equipment or to transmit a third signal to the infrastructure equipment, the third signal comprising information on the basis of which it is determinable whether or not a predetermined condition associated with the characteristic associated with the one or more second signals has been met.
    Type: Grant
    Filed: April 4, 2022
    Date of Patent: February 27, 2024
    Assignee: SONY GROUP CORPORATION
    Inventors: Martin Warwick Beale, Shin Horng Wong, Brian Alexander Martin, Basuki Priyanto, Nafiseh Mazloum
  • Patent number: 10877090
    Abstract: The terminals of a device under test are temporarily electrically connected to corresponding contact pads on a load board by a series of electrically conductive pin pairs. The pin pairs are held in place by an interposer membrane that includes a top contact plate facing the device under test, a bottom contact plate facing the load board, and a vertically resilient, non-conductive member between the top and bottom contact plates. Each pin pair includes a top and bottom pin, which extend beyond the top and bottom contact plates, respectively, toward the device under test and the load board, respectively. The top and bottom pins contact each other at an interface that is inclined with respect to the membrane surface normal. When compressed longitudinally, the pins translate toward each other by sliding along the interface. The sliding is largely longitudinal, with a small and desirable lateral component determined by the inclination of the interface.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: December 29, 2020
    Assignee: Johnstech International Corporation
    Inventors: John E. Nelson, Jeffrey C. Sherry, Patrick J. Alladio, Russell F. Oberg, Brian Warwick, Gary W. Michalko
  • Patent number: 10302675
    Abstract: The terminals of a device under test (DUT) are temporarily electrically connected to corresponding contact pads on a load board by a series of electrically conductive pin pairs. The pin pairs are held in place by an interposer membrane with a top facing the device under test, a bottom facing the load board, and a vertically resilient, non-conductive member between the top and bottom contact plates. Each pin pair includes a top and bottom pin, which extend beyond the top and bottom contact plates, respectively, toward the device under test and the load board, respectively. The bottom pins has a lower contact surface which includes an arcuate portion or ridge which increases contact pressure and ablates oxides by the rocking action of ridge when the DUT in inserted.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: May 28, 2019
    Assignee: Johnstech International Corporation
    Inventors: John E. Nelson, Jeffrey C. Sherry, Brian Warwick, Gary W. Michalko
  • Publication number: 20190004091
    Abstract: The terminals of a device under test (DUT) are temporarily electrically connected to corresponding contact pads on a load board by a series of electrically conductive pin pairs. The pin pairs are held in place by an interposer membrane with a top facing the device under test, a bottom facing the load board, and a vertically resilient, non-conductive member between the top and bottom contact plates. Each pin pair includes a top and bottom pin, which extend beyond the top and bottom contact plates, respectively, toward the device under test and the load board, respectively. The bottom pins has a lower contact surface which includes an arcuate portion or ridge which increases contact pressure and ablates oxides by the rocking action of ridge when the DUT in inserted.
    Type: Application
    Filed: September 10, 2018
    Publication date: January 3, 2019
    Inventors: John E. Nelson, Jeffrey C. Sherry, Brian Warwick, Gary W. Michalko
  • Patent number: 10073117
    Abstract: The terminals of a device under test (DUT) are temporarily electrically connected to corresponding contact pads on a load board by a series of electrically conductive pin pairs. The pin pairs are held in place by an interposer membrane with a top facing the device under test, a bottom facing the load board, and a vertically resilient, non-conductive member between the top and bottom contact plates. Each pin pair includes a top and bottom pin, which extend beyond the top and bottom contact plates, respectively, toward the device under test and the load board, respectively. The bottom pins has a lower contact surface which includes an arcuate portion or ridge which increases contact pressure and ablates oxides by the rocking action of ridge when the DUT in inserted.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: September 11, 2018
    Assignee: Johnstech International Corporation
    Inventors: John E. Nelson, Jeffrey C. Sherry, Brian Warwick, Gary W. Michalko
  • Publication number: 20170315169
    Abstract: The terminals of a device under test are temporarily electrically connected to corresponding contact pads on a load board by a series of electrically conductive pin pairs. The pin pairs are held in place by an interposer membrane that includes a top contact plate facing the device under test, a bottom contact plate facing the load board, and a vertically resilient, non-conductive member between the top and bottom contact plates. Each pin pair includes a top and bottom pin, which extend beyond the top and bottom contact plates, respectively, toward the device under test and the load board, respectively. The top and bottom pins contact each other at an interface that is inclined with respect to the membrane surface normal. When compressed longitudinally, the pins translate toward each other by sliding along the interface. The sliding is largely longitudinal, with a small and desirable lateral component determined by the inclination of the interface.
    Type: Application
    Filed: July 19, 2017
    Publication date: November 2, 2017
    Inventors: John E. Nelson, Jeffrey C. Sherry, Patrick J. Alladio, Russell F. Oberg, Brian Warwick, Gary W. Michalko
  • Publication number: 20170276699
    Abstract: The terminals of a device under test (DUT) are temporarily electrically connected to corresponding contact pads on a load board by a series of electrically conductive pin pairs. The pin pairs are held in place by an interposer membrane with a top facing the device under test, a bottom facing the load board, and a vertically resilient, non-conductive member between the top and bottom contact plates. Each pin pair includes a top and bottom pin, which extend beyond the top and bottom contact plates, respectively, toward the device under test and the load board, respectively. The bottom pins has a lower contact surface which includes an arcuate portion or ridge which increases contact pressure and ablates oxides by the rocking action of ridge when the DUT in inserted.
    Type: Application
    Filed: June 12, 2017
    Publication date: September 28, 2017
    Inventors: John E. Nelson, Jeffrey C. Sherry, Brian Warwick, Gary W. Michalko
  • Patent number: 9678106
    Abstract: The terminals of a device under test (DUT) are temporarily electrically connected to corresponding contact pads on a load board by a series of electrically conductive pin pairs. The pin pairs are held in place by an interposer membrane with a top facing the device under test, a bottom facing the load board, and a vertically resilient, non-conductive member between the top and bottom contact plates. Each pin pair includes a top and bottom pin, which extend beyond the top and bottom contact plates, respectively, toward the device under test and the load board, respectively. The bottom pins has a lower contact surface which includes an arcuate portion or ridge which increases contact pressure and ablates oxides by the rocking action of ridge when the DUT in inserted.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: June 13, 2017
    Assignee: Johnstech International Corporation
    Inventors: John E. Nelson, Jeffrey C. Sherry, Brian Warwick, Gary W. Michalko
  • Patent number: 9476936
    Abstract: The IC test system provides a system and method for thermal management of test pins. A test pin array (22) in a pin guide (24) is mounted in a retainer (20) which is located between an IC wafer (12) which contains IC devices to be tested (DUT) and a load board (40) which provides pathways to test signals to the DUT. On the other side of the load board is a contact plate (50) which together with the retainer straddles the load board. Leg extensions (36) pass through the load board apertures (42) and provide a thermal circuit from the contact plate to the retainer and to the pin array. On the upper side of the contact plate is a cooling/heating system with a thermal electric peltier device (62) and a further heat exchanger (64) as needed. Holes (44) are provided in the legs (36) to provide a supply of dry air to the wafer and pin array to minimize condensation as a result of cooling effects.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: October 25, 2016
    Assignee: Johnstech International Corporation
    Inventors: David Johnson, Jeffrey Sherry, Harlan Faller, Brian Warwick, Sarosh Patel, John Bucher, Jay Drescher
  • Publication number: 20160209444
    Abstract: The terminals of a device under test (DUT) are temporarily electrically connected to corresponding contact pads on a load board by a series of electrically conductive pin pairs. The pin pairs are held in place by an interposer membrane with a top facing the device under test, a bottom facing the load board, and a vertically resilient, non-conductive member between the top and bottom contact plates. Each pin pair includes a top and bottom pin, which extend beyond the top and bottom contact plates, respectively, toward the device under test and the load board, respectively. The bottom pins has a lower contact surface which includes an arcuate portion or ridge which increases contact pressure and ablates oxides by the rocking action of ridge when the DUT in inserted.
    Type: Application
    Filed: March 28, 2016
    Publication date: July 21, 2016
    Inventors: John E. Nelson, Jeffrey C. Sherry, Brian Warwick, Gary W. Michalko
  • Patent number: 9297832
    Abstract: The terminals of a device under test (DUT) are temporarily electrically connected to corresponding contact pads on a load board by a series of electrically conductive pin pairs. The pin pairs are held in place by an interposer membrane with a top facing the device under test, a bottom facing the load board, and a vertically resilient, non-conductive member between the top and bottom contact plates. Each pin pair includes a top and bottom pin, which extend beyond the top and bottom contact plates, respectively, toward the device under test and the load board, respectively. The bottom pins has a lower contact surface which includes an arcuate portion or ridge which increases contact pressure and ablates oxides by the rocking action of ridge when the DUT in inserted.
    Type: Grant
    Filed: May 27, 2014
    Date of Patent: March 29, 2016
    Assignee: Johnstech International Corporation
    Inventors: John E. Nelson, Jeffrey C. Sherry, Brian Warwick, Gary W. Michalko
  • Publication number: 20150123689
    Abstract: The terminals of a device under test are temporarily electrically connected to corresponding contact pads on a load board by a series of electrically conductive pin pairs. The pin pairs are held in place by an interposer membrane that includes a top contact plate facing the device under test, a bottom contact plate facing the load board, and a vertically resilient, non-conductive member between the top and bottom contact plates. Each pin pair includes a top and bottom pin, which extend beyond the top and bottom contact plates, respectively, toward the device under test and the load board, respectively. The top and bottom pins contact each other at an interface that is inclined with respect to the membrane surface normal. When compressed longitudinally, the pins translate toward each other by sliding along the interface.
    Type: Application
    Filed: January 12, 2015
    Publication date: May 7, 2015
    Inventors: John E. Nelson, Jeffrey C. Sherry, Patrick J. Alladio, Russell F. Oberg, Brian Warwick, Gary W. Michalko
  • Patent number: 9007082
    Abstract: The terminals of a device under test are temporarily electrically connected to corresponding contact pads on a load board by a series of electrically conductive pin pairs. The pin pairs are held in place by an interposer membrane that includes a top contact plate facing the device under test, a bottom contact plate facing the load board including a rocker base protrusion, and a vertically resilient, non-conductive member between the top and bottom contact plates. Each pin pair includes a top and bottom pin, which extend beyond the top and bottom contact plates, respectively, toward the device under test and the load board, respectively. The top and bottom pins contact each other at an interface that is inclined with respect to the membrane surface normal. When compressed longitudinally, the pins translate toward each other by sliding along the interface. The sliding is largely longitudinal, with a small and desirable lateral component determined by the inclination of the interface.
    Type: Grant
    Filed: June 20, 2012
    Date of Patent: April 14, 2015
    Assignee: Johnstech International Corporation
    Inventors: John E. Nelson, Jeffrey C. Sherry, Patrick J. Alladio, Russell F. Oberg, Brian Warwick, Gary W. Michalko
  • Patent number: 8937484
    Abstract: The terminals of a device under test are temporarily electrically connected to corresponding contact pads on a load board by a series of electrically conductive pin pairs. The pin pairs are held in place by an interposer membrane that includes a top contact plate facing the device under test, a bottom contact plate facing the load board, and a vertically resilient, non-conductive member between the top and bottom contact plates. Each pin pair includes a top and bottom pin, which extend beyond the top and bottom contact plates, respectively, toward the device under test and the load board, respectively. The top and bottom pins contact each other at an interface that is inclined with respect to the membrane surface normal. When compressed longitudinally, the pins translate toward each other by sliding along the interface. The sliding is largely longitudinal, with a small and desirable lateral component determined by the inclination of the interface.
    Type: Grant
    Filed: June 13, 2013
    Date of Patent: January 20, 2015
    Assignee: Johnstech International Corporation
    Inventors: John E. Nelson, Jeffrey C. Sherry, Patrick J. Alladio, Russell F. Oberg, Brian Warwick, Gary W. Michalko
  • Publication number: 20140266279
    Abstract: The terminals of a device under test (DUT) are temporarily electrically connected to corresponding contact pads on a load board by a series of electrically conductive pin pairs. The pin pairs are held in place by an interposer membrane with a top facing the device under test, a bottom facing the load board, and a vertically resilient, non-conductive member between the top and bottom contact plates. Each pin pair includes a top and bottom pin, which extend beyond the top and bottom contact plates, respectively, toward the device under test and the load board, respectively. The bottom pins has a lower contact surface which includes an arcuate portion or ridge which increases contact pressure and ablates oxides by the rocking action of ridge when the DUT in inserted.
    Type: Application
    Filed: May 27, 2014
    Publication date: September 18, 2014
    Applicant: Johnstech International Corporation
    Inventors: John E. Nelson, Jeffrey C. Sherry, Brian Warwick, Gary W. Michalko
  • Publication number: 20130271176
    Abstract: The terminals of a device under test are temporarily electrically connected to corresponding contact pads on a load board by a series of electrically conductive pin pairs. The pin pairs are held in place by an interposer membrane that includes a top contact plate facing the device under test, a bottom contact plate facing the load board, and a vertically resilient, non-conductive member between the top and bottom contact plates. Each pin pair includes a top and bottom pin, which extend beyond the top and bottom contact plates, respectively, toward the device under test and the load board, respectively. The top and bottom pins contact each other at an interface that is inclined with respect to the membrane surface normal. When compressed longitudinally, the pins translate toward each other by sliding along the interface. The sliding is largely longitudinal, with a small and desirable lateral component determined by the inclination of the interface.
    Type: Application
    Filed: June 13, 2013
    Publication date: October 17, 2013
    Inventors: John E. Nelson, Jeffrey C. Sherry, Patrick J. Alladio, Russell F. Oberg, Brian Warwick, Gary W. Michalko