Patents by Inventor Bruce Bateman
Bruce Bateman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9842639Abstract: Techniques are provided for managing voltages on memory cells in a cross-point array during a read operation. The techniques apply to vertical layer thyristor memory cells and non-thyristor memory cells. Voltages on selected bitlines (e.g., corresponding to memory cells from which data is to be read), are set to a read voltage level. Voltages on unselected bitlines (e.g., corresponding to memory cells from which data is not to be read and which are not to be disturbed) are set to a de-bias voltage level that is different from the read voltage level.Type: GrantFiled: October 7, 2016Date of Patent: December 12, 2017Assignee: Kilopass Technology, Inc.Inventors: Frank Guo, Bruce Bateman
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Patent number: 9653151Abstract: The access speeds of new memory technologies may not be compatible with product specifications of existing memory technologies such as DRAM, SRAM, and FLASH technologies. Their electrical parameters and behaviors are different such that they cannot meet existing memory core specifications without new architectures and designs to overcome their limitations. New memories such as STT-MRAM, Resistive-RAM, Phase-Change RAM, and a new class of memory called Vertical Layer Thyristor (VLT) RAM requires new read sensing and write circuits incorporating new voltage or current levels and timing controls to make these memory technologies work in today's systems. Systems and methods are provided for rendering the memory cores of these technologies transparent to existing peripheral logic so that they can be easily integrated.Type: GrantFiled: October 7, 2016Date of Patent: May 16, 2017Assignee: Kilopass Technology, Inc.Inventors: Adrian E. Ong, Bruce Bateman
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Patent number: 9419217Abstract: A method of manufacturing a memory structure includes forming a plurality of vertically-stacked horizontal line layers, interleaving a plurality of electrically conductive vertical lines with the electrically conductive horizontal lines, and forming a memory film at and between intersections of the electrically conductive vertical lines and the horizontal lines. In one embodiment of the invention, the electrically conductive vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines in each horizontal line layer. By configuring the electrically conductive vertical lines and electrically conductive horizontal lines so that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.Type: GrantFiled: August 15, 2012Date of Patent: August 16, 2016Assignee: UNITY SEMICONDUCTOR CORPORATIONInventors: Lidia Vereen, Bruce Bateman, David Eggleston, Louis Parrillo
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Patent number: 8943119Abstract: A system and a method are configured to improve the performance of general-purpose processors by implementing a functional unit that computes the product of a matrix operand with a vector operand, producing a vector result. The functional unit fully utilizes the entire resources of a 128 b by 128 b multiplier regardless of the operand size, as the number of elements of the matrix and vector operands increase as operand size is reduced. The unit performs both fixed-point and floating-point multiplications and additions with the highest-possible intermediate accuracy with modest resources.Type: GrantFiled: May 2, 2012Date of Patent: January 27, 2015Assignee: Microunity Systems Engineering, Inc.Inventors: Craig Hansen, Bruce Bateman, John Moussouris
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Patent number: 8937292Abstract: An ultra-high-density vertical cross-point array comprises a plurality of horizontal line layers having horizontal lines interleaved with a plurality of vertical lines arranged in rows and columns. The vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each consecutive pair of horizontal lines in each horizontal line layer. Each vertical line comprises a center conductor surrounded by a single or multi-layered memory film. Accordingly, when interleaved with the horizontal lines, two-terminal memory cells are integrally formed between the center conductor of each vertical line and each crossing horizontal line. By configuring the vertical and horizontal lines so that a row of vertical lines is positioned between each consecutive pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.Type: GrantFiled: August 15, 2011Date of Patent: January 20, 2015Assignee: Unity Semiconductor CorporationInventor: Bruce Bateman
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Patent number: 8891276Abstract: A memory array includes wordlines, local bitlines, two-terminal memory elements, global bitlines, and local-to-global bitline pass gates and gain stages. The memory elements are formed between the wordlines and local bitlines. Each local bitline is selectively coupled to an associated global bitline, by way of an associated local-to-global bitline pass gate. During a read operation when a memory element of a local bitline is selected to be read, a local-to-global gain stage is configured to amplify a signal on or passing through the local bitline to an amplified signal on or along an associated global bitline. The amplified signal, which in one embodiment is dependent on the resistive state of the selected memory element, is used to rapidly determine the memory state stored by the selected memory element.Type: GrantFiled: June 10, 2011Date of Patent: November 18, 2014Assignee: Unity Semiconductor CorporationInventors: Chang Hua Siau, Bruce Bateman
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Patent number: 8737151Abstract: A low read current architecture for memory. Bit lines of a cross point memory array are allowed to be charged by a selected word line until a minimum voltage differential between a memory state and a reference level is assured.Type: GrantFiled: October 4, 2011Date of Patent: May 27, 2014Assignee: Unity Semiconductor CorporationInventors: Bruce Bateman, Darrell Rinerson, Christophe Chevallier, Chang Hua Siau
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Patent number: 8610099Abstract: In an example, a single damascene structure is formed by, for example, providing a dielectric layer, forming a void in the dielectric layer, and forming a portion of a first two-terminal resistive memory cell and a portion of a second two-terminal resistive memory cell within the void. The portions of the two-terminal resistive memory cells may be vertically stacked within the void.Type: GrantFiled: August 15, 2012Date of Patent: December 17, 2013Assignee: Unity Semiconductor CorporationInventors: Lidia Vereen, Bruce Bateman, Louis Parrillo, Elizabeth Friend, David Eggleston
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Publication number: 20130207066Abstract: In an example, a single damascene structure is formed by, for example, providing a dielectric layer, forming a void in the dielectric layer, and forming a portion of a first two-terminal resistive memory cell and a portion of a second two-terminal resistive memory cell within the void. The portions of the two-terminal resistive memory cells may be vertically stacked within the void.Type: ApplicationFiled: August 15, 2012Publication date: August 15, 2013Applicant: Unity Semiconductor CorporationInventors: Lidia Vereen, Bruce Bateman, Louis Parrillo, Elizabeth Friend, David Eggleston
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Publication number: 20130210211Abstract: A method of manufacturing a memory structure includes forming a plurality of vertically-stacked horizontal line layers, interleaving a plurality of electrically conductive vertical lines with the electrically conductive horizontal lines, and forming a memory film at and between intersections of the electrically conductive vertical lines and the horizontal lines. In one embodiment of the invention, the electrically conductive vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines in each horizontal line layer. By configuring the electrically conductive vertical lines and electrically conductive horizontal lines so that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.Type: ApplicationFiled: August 15, 2012Publication date: August 15, 2013Inventors: Lidia Vereen, Bruce Bateman, David Eggleston, Louis Parrillo
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Publication number: 20130043455Abstract: An ultra-high-density vertical cross-point array comprises a plurality of horizontal line layers having horizontal lines interleaved with a plurality of vertical lines arranged in rows and columns. The vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each consecutive pair of horizontal lines in each horizontal line layer. Each vertical line comprises a center conductor surrounded by a single or multi-layered memory film. Accordingly, when interleaved with the horizontal lines, two-terminal memory cells are integrally formed between the center conductor of each vertical line and each crossing horizontal line. By configuring the vertical and horizontal lines so that a row of vertical lines is positioned between each consecutive pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.Type: ApplicationFiled: August 15, 2011Publication date: February 21, 2013Applicant: UNITY SEMICONDUCTOR CORPORATIONInventor: BRUCE BATEMAN
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Publication number: 20120314468Abstract: A memory array includes wordlines, local bitlines, two-terminal memory elements, global bitlines, and local-to-global bitline pass gates and gain stages. The memory elements are formed between the wordlines and local bitlines. Each local bitline is selectively coupled to an associated global bitline, by way of an associated local-to-global bitline pass gate. During a read operation when a memory element of a local bitline is selected to be read, a local-to-global gain stage is configured to amplify a signal on or passing through the local bitline to an amplified signal on or along an associated global bitline. The amplified signal, which in one embodiment is dependent on the resistive state of the selected memory element, is used to rapidly determine the memory state stored by the selected memory element.Type: ApplicationFiled: June 10, 2011Publication date: December 13, 2012Applicant: UNITY SEMICONDUCTOR CORPORATIONInventors: Chang Hua Siau, Bruce Bateman
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Publication number: 20120215826Abstract: The present invention provides a system and method for improving the performance of general-purpose processors by implementing a functional unit that computes the product of a matrix operand with a vector operand, producing a vector result. The functional unit fully utilizes the entire resources of a 128b by 128b multiplier regardless of the operand size, as the number of elements of the matrix and vector operands increase as operand size is reduced. The unit performs both fixed-point and floating-point multiplications and additions with the highest-possible intermediate accuracy with modest resources.Type: ApplicationFiled: May 2, 2012Publication date: August 23, 2012Applicant: Microunity Systems Engineering, Inc.Inventors: Craig Hansen, Bruce Bateman, John Moussouris
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Patent number: 8195735Abstract: The present invention provides a system and method for improving the performance of general-purpose processors by implementing a functional unit that computes the product of a matrix operand with a vector operand, producing a vector result. The functional unit fully utilizes the entire resources of a 128b by 128b multiplier regardless of the operand size, as the number of elements of the matrix and vector operands increase as operand size is reduced. The unit performs both fixed-point and floating-point multiplications and additions with the highest-possible intermediate accuracy with modest resources.Type: GrantFiled: December 9, 2008Date of Patent: June 5, 2012Assignee: Microunity Systems Engineering, Inc.Inventors: Craig Hansen, Bruce Bateman, John Moussouris
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Publication number: 20120075914Abstract: A low read current architecture for memory. Bit lines of a cross point memory array are allowed to be charged by a selected word line until a minimum voltage differential between a memory state and a reference level is assured.Type: ApplicationFiled: October 4, 2011Publication date: March 29, 2012Applicant: UNITY SEMICONDUCTOR CORPORATIONInventors: BRUCE BATEMAN, DARRELL RINERSON, CHRISTOPHE CHEVALLIER, CHANG HUA SIAU
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Patent number: 7800287Abstract: White-light efficiency from a light emitting diode is enhanced by recycling inwardly penetrating light outwardly by application of a multi-layer, thin film filter between the LED die and the phosphor layer. This procedure increases the package extraction efficiency.Type: GrantFiled: August 24, 2007Date of Patent: September 21, 2010Assignee: Osram Sylvania Inc.Inventors: Yi Zheng, Bruce Bateman, Matthew A. Stough, Madis Raukas
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Publication number: 20090094309Abstract: The present invention provides a system and method for improving the performance of general-purpose processors by implementing a functional unit that computes the product of a matrix operand with a vector operand, producing a vector result. The functional unit fully utilizes the entire resources of a 128b by 128b multiplier regardless of the operand size, as the number of elements of the matrix and vector operands increase as operand size is reduced. The unit performs both fixed-point and floating-point multiplications and additions with the highest-possible intermediate accuracy with modest resources.Type: ApplicationFiled: December 9, 2008Publication date: April 9, 2009Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.Inventors: Craig HANSEN, Bruce Bateman, John Moussouris
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Patent number: 7483935Abstract: The present invention provides a system and method for improving the performance of general-purpose processors by implementing a functional unit that computes the product of a matrix operand with a vector operand, producing a vector result. The functional unit fully utilizes the entire resources of a 128b by 128b multiplier regardless of the operand size, as the number of elements of the matrix and vector operands increase as operand size is reduced. The unit performs both fixed-point and floating-point multiplications and additions with the highest-possible intermediate accuracy with modest resources.Type: GrantFiled: September 4, 2002Date of Patent: January 27, 2009Assignee: Microunity Systems Engineering, Inc.Inventors: Craig Hansen, Bruce Bateman, John Moussouris
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Publication number: 20080054803Abstract: White-light efficiency from a light emitting diode is enhanced by recycling inwardly penetrating light outwardly by application of a multi-layer, thin film filter between the LED die and the phosphor layer. This procedure increases the package extraction efficiency.Type: ApplicationFiled: August 24, 2007Publication date: March 6, 2008Applicant: OSRAM SYLVANIA INC.Inventors: Yi Zheng, Bruce Bateman, Matthew A. Stough, Madis Raukas
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Patent number: D674848Type: GrantFiled: September 23, 2009Date of Patent: January 22, 2013Inventor: Bruce Bateman