Abstract: An apparatus includes a logical space and first and second physical spaces. The apparatus further includes a map in which first successive alternate logical elements of the logical space are mapped to successive adjacent physical elements of the first physical space, and second successive alternate logical elements of the logical space are mapped to successive adjacent physical elements of the second physical space. A control circuit employs the map to substantially concurrently manage storage of data extents into the first and second physical space by routing a first subset of the data extents into the first physical space, routing a second subset of the data extents into the second physical space, and splitting individual extents of a third subset of the data extents into sub-portions, with at least one of the sub-portions being routed to the first physical space and another sub-portion being routed to the second physical space.

Abstract: An iterative decoder is controlled to iteratively decode a block by performing one or more decoding iterations for the block. The iterative decoder uses a parity-check matrix and can be configured to process that parity-check matrix for parallel, sequential or a combination of parallel and sequential (“hybrid”) parity constraint updates.

Abstract: A three-dimensional magnetic recording media can consist of a single recording layer configured with three or more separate magnetization levels. A first magnetization level can be written to a selected region of said recording layer by applying a first write field to the grains of said region to form a “spin-up” magnetization in the grains of said region. A second magnetization level can be written by applying a second opposite write field to selected grains of said region to form a “spin-down” magnetization. At least a third intermediate magnetization level can be written by applying a weaker or alternating write field to grains of said region to form an intermediate magnetization comprising a mixture of spin-up and spin-down grains. By such method, said region may comprise a data bit capable of storing 3 or more units of information corresponding to the number of separate magnetization levels employed.

Abstract: A heat-assisted magnetic recording (HAMR) device includes transducer head comprising a heat source and a writer. The HAMR device further includes a power controller configured to selectively power on and off the heat source independent of current flowing through a write coil of the writer based on a position of the transducer head relative to an adjacent rotating media.

Abstract: An iterative decoder is controlled to iteratively decode a block by performing one or more decoding iterations for the block. The iterative decoder uses a parity-check matrix and can be configured to process that parity-check matrix for parallel, sequential or a combination of parallel and sequential (“hybrid”) parity constraint updates.

Abstract: Certain exemplary aspects of the present disclosure are directed towards methods and apparatuses in which logic circuitry generates an error detection code based on user data received from a host, and further generates a first set of check bits, to be written to the non-volatile memory circuit in conjunction with the user data, by combining the error detection code with a hashed data address of the user data. In some embodiments, the check bits associated with the user data providing verification that the user data was written in the appropriate physical block address of the non-volatile memory circuit.

Abstract: Transmission signals may generated based on three differential signals and transmitted along a channel. Each of the plurality of transmission signals may include a signal representative of each of the three differential signals. After receiving the transmission signals, the original three differential signals may be generated based on the transmission signals.

Abstract: An iterative decoder is controlled to iteratively decode a block by performing one or more decoding iterations for the block. The iterative decoder uses a parity-check matrix and can be configured to process that parity-check matrix for parallel, sequential or a combination of parallel and sequential (“hybrid”) parity constraint updates.

Abstract: Transmission signals may generated based on three differential signals and transmitted along a channel. Each of the plurality of transmission signals may include a signal representative of each of the three differential signals. After receiving the transmission signals, the original three differential signals may be generated based on the transmission signals.

Abstract: Apparatus for providing skew compensation in a patterned medium, such as but not limited to a self-assembling bit patterned medium. In accordance with some embodiments, the apparatus includes a transducer and a rotatable substrate. The substrate has a plurality of rows of spaced apart data recording dots. Each row of dots is angularly offset from an immediately adjacent row responsive to a skew angle of the transducer. The rows of dots are arranged into concentric zones of hypertracks. Each zone has an arcuate timing field segment which extends across the zone and is angularly discontinuous with the timing field segment of an immediately adjacent zone.

Abstract: Certain exemplary aspects of the present disclosure are directed towards methods and apparatuses in which logic circuitry generates an error detection code based on user data received from a host, and further generates a first set of check bits, to be written to the non-volatile memory circuit in conjunction with the user data, by combining the error detection code with a hashed data address of the user data. In some embodiments, the check bits associated with the user data providing verification that the user data was written in the appropriate physical block address of the non-volatile memory circuit.

Abstract: Compensation for template misalignment and offset induced eccentricity errors for a multi-template patterned medium, such as a bit patterned medium (BPM) used to record data in a data storage device. In some embodiments, a rotatable patterned data recording medium has a plurality of concentric tracks, each track having data fields interspersed with servo fields and timing fields. A data transducer senses the respective data, servo and timing fields on a target track. A disc-locked clock (DLC) circuit generates separate servo clock and data clock signals that are frequency modulated responsive to variations in locations of the timing fields.

Abstract: The embodiments disclose an analyzer configured to determine positions of circumferential gratings track features and alignment patterns in a first template and a phase device configured to determine positions of radial gratings features and interspersed pattern fields in a second template, wherein the first template is transferred and cross-imprinted with the second template features and patterns to form a third template substrate as a rectangular patterned stack imprint template.

Abstract: Apparatus for providing skew compensation in a patterned medium, such as but not limited to a self-assembling bit patterned medium. In accordance with some embodiments, the apparatus includes a transducer and a rotatable substrate. The substrate has a plurality of rows of spaced apart data recording dots. Each row of dots is angularly offset from an immediately adjacent row responsive to a skew angle of the transducer. The rows of dots are arranged into concentric zones of hypertracks. Each zone has an arcuate timing field segment which extends across the zone and is angularly discontinuous with the timing field segment of an immediately adjacent zone.

Abstract: Methods and systems involve collecting memory device parameters and using memory device parameters to determine memory wear information. A set of first parameters associated with wear of the memory device is monitored for at least one memory unit of the memory device. The first parameters are compared to respective trigger criterion. If the comparison reveals that one or more of the first parameters are beyond their trigger criterion, then collection of a second set of parameters is triggered. The second parameters are also indicative of the wear of the memory device. The set of first parameters may overlap the set of second parameters. The set of second parameters are used to develop memory wear information. In some implementations, the memory wear information may be configuration information used to configure the read/write channel to compensate for wear of the memory device. In some implementations, the memory wear information may be used to predict or estimate the lifetime of the device.

Abstract: Methods and systems involve collecting memory device parameters and using memory device parameters to determine memory wear information. A set of first parameters associated with wear of the memory device is monitored for at least one memory unit of the memory device. The first parameters are compared to respective trigger criterion. If the comparison reveals that one or more of the first parameters are beyond their trigger criterion, then collection of a second set of parameters is triggered. The second parameters are also indicative of the wear of the memory device. The set of first parameters may overlap the set of second parameters. The set of second parameters are used to develop memory wear information. In some implementations, the memory wear information may be configuration information used to configure the read/write channel to compensate for wear of the memory device. In some implementations, the memory wear information may be used to predict or estimate the lifetime of the device.

Abstract: Approaches for decoding data read from memory cells of a nonvolatile, solid state memory involve attempting to decode hard data using a hard decoding process prior to a time that soft data is available to the decoder. The hard data includes information about the digital symbols stored in the memory cells without data confidence information. The soft data includes information about the digital symbols stored in the memory cells and data confidence information. In response to the hard decoding process failing to achieve convergence, after the soft data becomes available to the decoder, the soft data is decoded using a soft decoding process. The decoder generates an output of the decoded data after the hard decoding process or the soft decoding process achieves convergence.

Abstract: A nominal reference read operation compares analog voltages of the memory cells to at least one nominal reference voltage. A shifted reference read operation compares the analog voltages of the memory cells to at least one shifted reference voltage that is shifted from the nominal reference voltage to compensate for an expected change in the analog voltages of the memory cells. Data stored in the memory cells is decoded by a first decoding process that uses the information from either the nominal reference read operation or the shifted reference read operation. The data stored in the memory cells is decoded by a second decoding process that uses the information from both the nominal reference read operation and the shifted reference read operation.

Abstract: Multiple logical pages are jointly encoded into a single code word and are stored in the same physical page of a solid state non-volatile memory (NVM) device having multi-level memory cells. A first logical page of the multiple logical pages is stored in the memory device as first bits of the multi-level memory cells while a second logical page of the multiple logical pages is temporarily cached. After the first logical page is stored as the first bits of the memory cell, the second logical page is stored as second bits of the memory cells.

Abstract: Methods, circuits, and disk drive that correct errors in data that is temporarily stored in a memory buffer are disclosed. An error detection code and an error correction code are generated for data. The data, the error detection code, and the error correction code are stored in the memory buffer. The data is retrieved from the memory buffer and error detected using the error detection code. In response to detecting an error, the error correction code is applied to the retrieved data to generate corrected data.