Abstract: A compliant pin system includes a pin having a compliant section including a first leg and an opposing second leg. A first plurality of contact members extend along the first leg. A second plurality of contact members extend along the second leg. A pin validation system is operatively connected to the first plurality of contact members and the second plurality of contact members. The pin validation system detects a presence of an electrical signal passing between corresponding pairs of the first plurality of contact members and the second plurality of contact members to determine an integrity of the compliant pin.

Abstract: A stubless via in printed wiring board may comprise one or more core layers. At least one core layer may be circuitized by including a copper trace and at least two other core layers may include copper laminations. The stubless via may further comprise one or more prepreg layers. The prepreg layers may be alternatively stacked between the core layers. the stubless via may further comprise a via. the via may be drilled through each of the alternatively stacked prepreg layers and core layers, exposing internal portions of the prepreg layers and core layers drilled through.

Abstract: A PWB may be drilled forming a via. The via may expose one or more internal portions of a core layer, a prepreg layer, and an anti-plate coating. A seed material may then be applied from a top portion of the PWB to the via, forming a seed layer in the via, the seed material not adhering to the anti-plate coating. Electroless metal may then be applied from the top portion of the PWB to the via, forming an electroless plate layer that adheres to the seed layer. Electrolytic copper may then be applied from the top portion of the PWB to the via, forming a copper layer that adheres to the electroless plate layer. A bottom portion of the electroless plate layer may then be removed.

Abstract: A compliant pin system includes a pin having a compliant section including a first leg and an opposing second leg. A first plurality of contact members extend along the first leg. A second plurality of contact members extend along the second leg. A pin validation system is operatively connected to the first plurality of contact members and the second plurality of contact members. The pin validation system detects a presence of an electrical signal passing between corresponding pairs of the first plurality of contact members and the second plurality of contact members to determine an integrity of the compliant pin.

Abstract: A PWB may be drilled forming a via. The via may expose one or more internal portions of a core layer, a prepreg layer, and an anti-plate coating. A seed material may then be applied from a top portion of the PWB to the via, forming a seed layer in the via, the seed material not adhering to the anti-plate coating. Electroless metal may then be applied from the top portion of the PWB to the via, forming an electroless plate layer that adheres to the seed layer. Electrolytic copper may then be applied from the top portion of the PWB to the via, forming a copper layer that adheres to the electroless plate layer. A bottom portion of the electroless plate layer may then be removed.

Abstract: A stubless via in printed wiring board may comprise one or more core layers. At least one core layer may be circuitized by including a copper trace and at least two other core layers may include copper laminations. The stubless via may further comprise one or more prepreg layers. The prepreg layers may be alternatively stacked between the core layers. the stubless via may further comprise a via. the via may be drilled through each of the alternatively stacked prepreg layers and core layers, exposing internal portions of the prepreg layers and core layers drilled through.

Abstract: A PWB may be drilled forming a via. The via may expose one or more internal portions of a core layer, a prepreg layer, and an anti-plate coating. A seed material may then be applied from a top portion of the PWB to the via, forming a seed layer in the via, the seed material not adhering to the anti-plate coating. Electroless metal may then be applied from the top portion of the PWB to the via, forming an electroless plate layer that adheres to the seed layer. Electrolytic copper may then be applied from the top portion of the PWB to the via, forming a copper layer that adheres to the electroless plate layer. A bottom portion of the electroless plate layer may then be removed.

Abstract: The present invention relates to computer hardware design and in particular to a printed circuit board comprising wiring dedicated to supply electric board components such as integrated circuits with at least three different reference planes. In order to provide a printed circuit board having an improved signal return path for basically all relevant signal layers at transitions between card, connector, module and chip while still holding the cross-section structure simple, it is proposed to establish a layer structure wherein a) a split voltage plane is located adjacent to one side of one of said reference planes and comprises conducting portions for all of said at least three different voltage levels in respective plane parts, and b) a signal layer being located adjacent to said reference planes.

Abstract: The present invention relates to computer hardware design, and in particular to a printed circuit board (card) comprising wiring dedicated to supply electric board components such as integrated circuits with at least three different reference planes. In particular at locations, where the pins of a card-to-card connector enter the layer structure of the card discontinuities brake the high frequency signal return path of a given signal wiring. In order to close the signal return path around a signal path from card to card including the connector, and thus to limit the signal coupling while concurrently keeping the card design as simple as possible, it is proposed to provide a) an additional capacitance for a given signal wiring in a discontinuity section, b) wherein the additional capacitance is formed by a voltage island placed within a signal layer located next to the given signal wiring.

Abstract: A method and structure is disclosed for forming a removable interconnect for semiconductor packages, where the connector is adapted to repeatedly change from a first shape into a second shape upon being subjected to a temperature change and to repeatedly return to the first shape when not being subjected to the temperature change. The connector can be disconnected when the connector is in its second shape and the connector cannot be disconnected when the connector is in its first shape.

Abstract: A method and structure is disclosed for forming a removable interconnect for semiconductor packages, where the connector is adapted to repeatedly change from a first shape into a second shape upon being subjected to a temperature change and to repeatedly return to the first shape when not being subjected to the temperature change. The connector can be disconnected when the connector is in its second shape and the connector cannot be disconnected when the connector is in its first shape.

Abstract: An apparatus and method for at least one of detecting and preventing burning of a PCB is disclosed. The method comprises configuring a first comb array defined by a plurality of first fingers at a first potential; configuring a second comb array defined by a plurality of second fingers at a second potential different from the first potential; interlacing the plurality of first fingers defining the first comb array with the plurality of second fingers defining the second comb array embedded in a substrate; disposing the substrate with the PCB; and detecting a rise in leakage current between the first and second comb arrays indicative of a breakdown of the substrate.

Abstract: A method and structures are provided for implementing enhanced reliability for printed circuit board high power dissipation applications. An external return current member provides a return current path outside of the printed circuit board, thereby minimizing power dissipation within the printed circuit board. The external return current member can be implemented with an associated stiffener formed of electrically conductive material. Alternatively, the external return current member can be implemented with a sheet of electrically conductive material with an insulator provided between the sheet and the associated stiffener.

Abstract: A method to replace an electrical interface on a printed circuit board having a plurality of contact pads on a top surface, the contact pads being connected to conducting material extending through said circuit board. For the contact pad being replaced, drilling a hole through said printed circuit board at that location, and removing any remaining conductor material attached to the contact pad on the top board surface. Providing a replacement conductor/contact pad structure having a generally T-configuration with a stem and a head that completely surrounds the stem, wherein said head has a diameter greater than the diameter of the drilled hole. Inserting the replacement conductor/contact pad into the hole with said stem extending beyond the second surface of the board with the bottom surface of the head being in contact with the first surface of said board. A replacement conductor/contact pad on repaired board is also described.

Abstract: A compliant pin contact and assembly utilizing same in which the contact is comprised of two layers, each of a different material and coefficient of thermal expansion (CTE) than the other, to enable insertion within an opening in either a “cold” or “hot” state to thereby expand and positively engage the opening's walls, thereby securedly holding the pin in position. Representative materials include Invar and aluminum.

Abstract: Described is a method for minimizing switching noise in the high- and mid-frequency range on printed circuit cards or boards by means of a plurality of surface mounted decoupling capacitors. A novel configuration and implementation of capacitor pads including the connecting vias is also presented. As a result the parasitic inductance of the pads and vias can be significantly reduced. Thus the effectiveness of the decoupling capacitors in the mid and high frequency range can be increased, the voltage drop can be reduced and the system performance can be increased. Several design rules for the new pad via configuration lead to the significant reduction of the parasitic inductance. The proposal is especially important for high integrated system designs on boards and cards combined with increased cycle times.

Abstract: A compliant pin contact and assembly utilizing same in which the contact is comprised of two layers, each of a different material and coefficient of thermal expansion (CTE) than the other, to enable insertion within an opening in either a “cold” or “hot” state to thereby expand and positively engage the opening's walls, thereby securedly holding the pin in position. Representative materials include Invar and aluminum.

Abstract: Described is a method for minimizing switching noise in the high- and mid-frequency range on printed circuit cards or boards by means of a plurality of surface mounted decoupling capacitors. A novel configuration and implementation of capacitor pads including the connecting vias is also presented. As a result the parasitic inductance of the pads and vias can be significantly reduced. Thus the effectiveness of the decoupling capacitors in the mid and high frequency range can be increased, the voltage drop can be reduced and the system performance can be increased. Several design rules for the new pad via configuration lead to the significant reduction of the parasitic inductance. The proposal is especially important for high integrated system designs on boards and cards combined with increased cycle times.

Abstract: An apparatus and method for fabricating integral three-dimensional objects from contiguous layers of a photosensitive composition in an imagewise manner, with an additional photogelled portion or photohardened wall, or both, surrounding the three-dimensional object.