Abstract: A phase-locked loop (PLL) filter of a read channel includes a filter portion having an input coupled to delay circuitry having an output. The input of the filter portion is configured to receive a phase error signal. A look-up table is coupled to the filter portion. The look-up table comprises phase coefficients and frequency coefficients associated with a plurality of phase error magnitudes. The look-up table is configured to provide one or both of a selected phase coefficient and a selected frequency coefficient based on a magnitude of the phase error signal. The PLL filter is configured to adjust a bandwidth of the filter portion using one or both of the selected phase coefficient and the selected frequency coefficient. A phase signal indicative of estimated phase disturbance is produced at the output of the delay circuitry.

Abstract: A pattern of features of a storage medium includes first features having a first logical state and second features having a second logical state, wherein a cross track dimension of the first features is different from a cross track dimension of the second features. A transducer of a memory device senses the pattern of features and generates a transducer signal. Read circuitry samples the transducer signal at a frequency of a sampling clock signal and generates a read signal from the sampled transducer signal. Servo electronics includes a demodulator that demodulates at least first and second orthogonal frequency components of the read signal. Timing circuitry synchronizes a phase of the sampling clock signal with a phase of the pattern of features using the first orthogonal frequency component. Position error circuitry generates a signal indicating a cross track positional offset of the transducer relative to the features using the first and second orthogonal frequency components.

Abstract: A pattern of features of a storage medium includes first features having a first logical state and second features having a second logical state, wherein a cross track dimension of the first features is different from a cross track dimension of the second features. A transducer of a memory device senses the pattern of features and generates a transducer signal. Read circuitry samples the transducer signal at a frequency of a sampling clock signal and generates a read signal from the sampled transducer signal. Servo electronics includes a demodulator that demodulates at least first and second orthogonal frequency components of the read signal. Timing circuitry synchronizes a phase of the sampling clock signal with a phase of the pattern of features using the first orthogonal frequency component. Position error circuitry generates a signal indicating a cross track positional offset of the transducer relative to the features using the first and second orthogonal frequency components.

Abstract: A circuit may be configured to reduce the amount of space used on a storage device when a transducer having a reader and writer passes from a writable data field to a read-only field by enabling both the reader and writer simultaneously. The circuit can be configured to reduce to a threshold level the noise on a read signal that can occur when the reader is over a read-only field and the writer is over a writable data field, and can ignore the read data when both the writer and reader are enabled simultaneously over a writable data field.

Abstract: Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a memory has a plurality of solid-state non-volatile memory cells. A processing circuit is connected to the memory and configured to direct the execution of a plurality of read error recovery routines in response to at least one uncorrectable read error in a data set retrieved from the memory. The recovery routines are executed in a selected order based on an elapsed recovery time parameter for each of the recovery routines and an estimated probability of success of each of the recovery routines.

Abstract: Systems and methods are included for determining a presence of an upcoming reading field during a write mode of a storage device, and initiating a read-while write RWW) mode of the storage device in response to the sensed reading field. Initiating the RWW mode comprises warming up the reader circuitry, generating a signal in response to an end to the write operation, and activating reader bias current in response to the generated signal.

Abstract: Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, the apparatus has a solid-state non-volatile memory and a processing circuit configured to write data to a selected location of the memory. The data are arranged in the form of multi-bit code words each comprising a user data payload and associated parity data configured to correct one or more bit errors in the user data payload. The processing circuit adjusts at least a selected one of a size of the code words, a size of the user data payloads or a size of the parity data responsive to at least a selected one of an accumulated count of access operations upon the selected location or an error rate associated with the selected location.

Abstract: Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a non-volatile memory is arranged into a plurality of blocks, with each of the blocks constituting an integral plural number N of fixed-sized, multi-bit transfer units. A processing circuit retrieves at least a portion of the data stored in a selected block to a volatile memory buffer in response to a transfer unit (TU) bit map. The TU bit map is stored in a memory and provides a multi-bit sequence of bits corresponding to the N transfer units of the selected block. The values of the bits in the multi-bit sequence of bits indicate whether the corresponding transfer units are to be retrieved.

Abstract: A pattern of features of a storage medium includes first features having a first logical state and second features having a second logical state, wherein a cross track dimension of the first features is different from a cross track dimension of the second features. A transducer of a memory device senses the pattern of features and generates a transducer signal. Read circuitry samples the transducer signal at a frequency of a sampling clock signal and generates a read signal from the sampled transducer signal. Servo electronics includes a demodulator that demodulates at least first and second orthogonal frequency components of the read signal. Timing circuitry synchronizes a phase of the sampling clock signal with a phase of the pattern of features using the first orthogonal frequency component. Position error circuitry generates a signal indicating a cross track positional offset of the transducer relative to the features using the first and second orthogonal frequency components.

Abstract: An apparatus includes a write element configured to apply a magnetic field to write data on a portion of a heat-assisted magnetic recording media in response to an energizing current. An energy source is configured to heat the portion of the media being magnetized by the write element. A preheat energizing current is applied to the write element during an interval before writing the data to the portion of the media. The preheat energizing current does not cause data to be written to the media and brings at least one of the write element and driver circuitry into thermal equilibrium prior to writing the data on the portion.

Abstract: Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a memory has a plurality of solid-state non-volatile memory cells. A processing circuit is connected to the memory and configured to direct the execution of a plurality of read error recovery routines in response to at least one uncorrectable read error in a data set retrieved from the memory. The recovery routines are executed in a selected order based on an elapsed recovery time parameter for each of the recovery routines and an estimated probability of success of each of the recovery routines.

Abstract: Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, the apparatus has a solid-state non-volatile memory and a processing circuit configured to write data to a selected location of the memory. The data are arranged in the form of multi-bit code words each comprising a user data payload and associated parity data configured to correct one or more bit errors in the user data payload. The processing circuit adjusts at least a selected one of a size of the code words, a size of the user data payloads or a size of the parity data responsive to at least a selected one of an accumulated count of access operations upon the selected location or an error rate associated with the selected location.

Abstract: Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a non-volatile memory is arranged into a plurality of blocks, with each of the blocks constituting an integral plural number N of fixed-sized, multi-bit transfer units. A processing circuit retrieves at least a portion of the data stored in a selected block to a volatile memory buffer in response to a transfer unit (TU) bit map. The TU bit map is stored in a memory and provides a multi-bit sequence of bits corresponding to the N transfer units of the selected block. The values of the bits in the multi-bit sequence of bits indicate whether the corresponding transfer units are to be retrieved.

Abstract: Systems and methods are included for determining a presence of an upcoming reading field during a write mode of a storage device, and initiating a read-while write (RWW) mode of the storage device in response to the sensed reading field. Initiating the RWW mode comprises warming up the reader circuitry, generating a signal in response to an end to the write operation, and activating reader bias current in response to the generated signal.

Abstract: Systems and methods are included for determining a presence of an upcoming reading field during a write mode of a storage device, and initiating a read-while write (RWW) mode of the storage device in response to the sensed reading field. Initiating the RWW mode comprises warming up the reader circuitry, generating a signal in response to an end to the write operation, and activating reader bias current in response to the generated signal.

Abstract: A memory system includes a storage medium having tracks arranged on the storage medium. The tracks include data track portions configured to store data. The tracks have a data track width and offset correction portions having a width that is greater than the data track width of the associated data track. Each offset correction portion stores one or both of positional offset correction values and timing offset correction values. The positional offset correction values are configured to correct for errors that occur in cross track positioning relative to the medium and the timing offset correction values are configured to correct for errors that occur in down track timing relative to the medium.

Abstract: Random numbers are generated using entropic properties associated with circuit hardware. Consistent with one method, a switching voltage regulator circuit is used to generate a random number. Data that is responsive to switching states of the switching voltage regulator circuit is generated. A multi-bit random number is then generated from the generated data.

Abstract: A memory system includes a storage medium having tracks arranged on the storage medium. The tracks include data track portions configured to store data. The tracks have a data track width and offset correction portions having a width that is greater than the data track width of the associated data track. Each offset correction portion stores one or both of positional offset correction values and timing offset correction values. The positional offset correction values are configured to correct for errors that occur in cross track positioning relative to the medium and the timing offset correction values are configured to correct for errors that occur in down track timing relative to the medium.

Abstract: A data storage medium has first and second data sectors of a track, a pre-servo gap being proximate the first data sector. The data storage medium also includes a servo wedge that stores servo data for the track. A start of the servo wedge is proximate to the pre-servo-gap and an end of the servo wedge is proximate to the second data sector. A repeatable runout field is included in the pre-servo gap.

Abstract: Approaches for determining the timing latency of a communication path are described. Some embodiments involve a method for testing timing latency. A signal is driven on a first data path and is returned through a second data path through a loop back element. The timing latency of at least a portion of the communication path that includes the first data path and the second data path is tested using the signal returned on the second data path. The gain of the second data path is adjusted to a test value during the testing of the timing latency.