Abstract: A memory chip, comprising a chip memory section organized to hold a plurality of separate blocks of data, with each of the data blocks containing M individual data units; a circuit for addressing a given block of data in the chip memory section; and an N data unit chip parallel output interface from the memory chip where N is less than M, and N is greater than one. The memory chip further comprises a chip register for receiving from the chip memory section at least a portion of an addressed block of data, which portion comprises P data units, where P is greater than N, the chip register having P register stages for holding the P data units of the addressed data block, wherein the P register stages are grouped into at least a first and second groups of stages, with no group of stages comprising more than N register stages and with at least one of the groups of register stages having a plurality of stages.

Abstract: An apparatus and method whereby a static column mode DRAM can access a unique data bit located anywhere within the array chip and sustain a continuous transfer of requested bits in a contiguous group of bits (i.e. block). Steering of the data in a prescribed order is accomplished via a special steering and gating network. A control line, toggle, is used on both rising and falling edges to produce this gapless transfer.

Abstract: A CCD recirculating memory system is disclosed in which "partially good" CCD memory chips and "all good" memory chips are mounted on memory cards. The defective portions of the partially good chips are in the same chip octants on the same card. The cards are addressed by address permutation means which causes the defective portions to appear to have the same predetermined address to the operating system.The addressed CCD row on the partially good chips are clocked at a fast rate while the unaddressed rows are clocked at a slow rate. All of the rows of the "all good" chips are clocked at a fast rate when a defective portion of the partially good chips is being addressed and are otherwise clocked at a slow rate.A select signal is generated whenever the predetermined address is invoked and causes the substitution of an all good chip for the addressed partially good chip.

Abstract: Apparatus is disclosed for quickly testing memory arrays of multiple recirculating loop memory elements and for locating faulty elements, if any, within designated subdivisions of said array. All loops are loaded with identical test bits. The loaded data is verified and faulty elements, if any, are located by means of a plurality of comparison AND gates. Each gate is connected to the output of a respective subdivision of the array elements and produces a first output signal when all such outputs are identical (on a serial bit-by-bit basis) and produces a second output signal when all said outputs are not identical. The output signals from the respective comparison AND gates are sensed in serial succession to locate the array subdivision containing any faulty elements.