Patents by Inventor Bruce E. Byrkett
Bruce E. Byrkett has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11105851Abstract: A microcontroller comprises a plurality of digital peripheral blocks and a direct memory access (DMA) controller coupled thereto. The plurality of digital peripheral blocks includes a digital peripheral block that is configured to issue a DMA request. Upon receipt of the DMA request, the DMA controller is configured to retrieve configuration information and to write the configuration information to a configuration register associated with a circuit element of the microcontroller.Type: GrantFiled: March 17, 2020Date of Patent: August 31, 2021Assignee: Cypress Semiconductor CorporationInventors: Harold Kutz, Timothy John Williams, Bert Sullam, Warren S. Snyder, James H. Shutt, Bruce E. Byrkett, Monte Mar, Eashwar Thiagarajan, Nathan Wayne Kohagen, David G. Wright, Mark E Hastings, Dennis R. Seguine
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Patent number: 11088692Abstract: A programmable input/output (I/O) circuit includes an output buffer coupled between an output signal and an I/O pad and an input comparator coupled between an input signal and the I/O pad. The input comparator includes a first input coupled to the I/O pad. A multiplexor receives a select signal for selecting a first reference voltage from the plurality of reference voltages at a first time and for dynamically selecting a second reference voltage from the plurality of reference voltages at a second time.Type: GrantFiled: April 29, 2020Date of Patent: August 10, 2021Assignee: Cypress Semiconductor CorporationInventors: Timothy John Williams, David G. Wright, Gregory John Verge, Bruce E. Byrkett
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Publication number: 20200321963Abstract: A programmable input/output (I/O) circuit includes an output buffer coupled between an output signal and an I/O pad and an input comparator coupled between an input signal and the I/O pad. The input comparator includes a first input coupled to the I/O pad. A multiplexor receives a select signal for selecting a first reference voltage from the plurality of reference voltages at a first time and for dynamically selecting a second reference voltage from the plurality of reference voltages at a second time.Type: ApplicationFiled: April 29, 2020Publication date: October 8, 2020Applicant: Cypress Semiconductor CorporationInventors: Timothy John Williams, David G. Wright, Gregory John Verge, Bruce E. Byrkett
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Publication number: 20200300910Abstract: A microcontroller comprises a plurality of digital peripheral blocks and a direct memory access (DMA) controller coupled thereto. The plurality of digital peripheral blocks includes a digital peripheral block that is configured to issue a DMA request. Upon receipt of the DMA request, the DMA controller is configured to retrieve configuration information and to write the configuration information to a configuration register associated with a circuit element of the microcontroller.Type: ApplicationFiled: March 17, 2020Publication date: September 24, 2020Applicant: Cypress Semiconductor CorporationInventors: Harold Kutz, Timothy John Williams, Bert Sullam, Warren S. Snyder, James H. Shutt, Bruce E. Byrkett, Monte Mar, Eashwar Thiagarajan, Nathan Wayne Kohagen, David G. Wright, Mark E Hastings, Dennis R. Seguine
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Patent number: 10666258Abstract: A programmable input/output (I/O) circuit includes an output buffer coupled between an output signal and an I/O pad and an input comparator coupled between an input signal and the I/O pad. The input comparator includes a first input coupled to the I/O pad. A multiplexor receives a select signal for selecting a first reference voltage from the plurality of reference voltages at a first time and for dynamically selecting a second reference voltage from the plurality of reference voltages at a second time.Type: GrantFiled: November 16, 2018Date of Patent: May 26, 2020Assignee: Cypress Semiconductor CorporationInventors: Timothy John Williams, David G. Wright, Gregory John Verge, Bruce E. Byrkett
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Patent number: 10634722Abstract: A programmable device comprises a plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, and a power manger coupled with the plurality of programmable blocks. The power manager is configured to supply power to a subset of the plurality of programmable blocks during debugging of the subset while maintaining a different subset of the plurality of programmable blocks in a lower power mode.Type: GrantFiled: May 23, 2019Date of Patent: April 28, 2020Assignee: Cypress Semiconductor CorporationInventors: Harold Kutz, Timothy John Williams, Bert Sullam, Warren S. Snyder, James H. Shutt, Bruce E. Byrkett, Monte Mar, Eashwar Thiagarajan, Nathan Wayne Kohagen, David G. Wright, Mark E Hastings, Dennis R. Seguine
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Publication number: 20190214990Abstract: A programmable input/output (I/O) circuit includes an output buffer coupled between an output signal and an I/O pad and an input comparator coupled between an input signal and the I/O pad. The input comparator includes a first input coupled to the I/O pad. A multiplexor receives a select signal for selecting a first reference voltage from the plurality of reference voltages at a first time and for dynamically selecting a second reference voltage from the plurality of reference voltages at a second time.Type: ApplicationFiled: November 16, 2018Publication date: July 11, 2019Applicant: Cypress Semiconductor CorporationInventors: Timothy John Williams, David G. Wright, Gregory John Verge, Bruce E. Byrkett
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Patent number: 10345377Abstract: A programmable device comprises a plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, and a power manger coupled with the plurality of programmable blocks. The power manager is configured to supply power to a subset of the plurality of programmable blocks during debugging of the subset while maintaining a different subset of the plurality of programmable blocks in a lower power mode.Type: GrantFiled: April 3, 2018Date of Patent: July 9, 2019Assignee: Cypress Semiconductor CorporationInventors: Harold M. Kutz, Timothy John Williams, Bert S. Sullam, Warren S. Snyder, James H. Shutt, Bruce E. Byrkett, Monte Mar, Eashwar Thiagarajan, Nathan Wayne Kohagen, David G. Wright, Mark E. Hastings, Dennis R. Seguine
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Patent number: 10153770Abstract: A apparatus, having a processing system and an input buffer coupled with both the processing system and one of two IO pads, and a reference buffer coupled to both the input buffer and the second of the IO pads such that the reference generator controls the input threshold of the input buffer in response to an analog voltage received from an external circuit on the second of the IO pads.Type: GrantFiled: December 5, 2016Date of Patent: December 11, 2018Assignee: Cypress Semiconductor CorporationInventors: Timothy John Williams, David G. Wright, Gregory John Verge, Bruce E. Byrkett
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Publication number: 20180292454Abstract: A programmable device comprises a plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, and a power manger coupled with the plurality of programmable blocks. The power manager is configured to supply power to a subset of the plurality of programmable blocks during debugging of the subset while maintaining a different subset of the plurality of programmable blocks in a lower power mode.Type: ApplicationFiled: April 3, 2018Publication date: October 11, 2018Applicant: Cypress Semiconductor CorporationInventors: Harold M. Kutz, Timothy John Williams, Bert S. Sullam, Warren S. Snyder, James H. Shutt, Bruce E. Byrkett, Monte Mar, Eashwar Thiagarajan, Nathan Wayne Kohagen, David G. Wright, Mark E Hastings, Dennis R. Seguine
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Patent number: 9952282Abstract: A programmable device comprises a plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, and a power manager coupled with the plurality of programmable blocks. The power manager is configured to supply power to a subset of the plurality of programmable blocks during debugging of the subset while maintaining a different subset of the plurality of programmable blocks in a lower power mode.Type: GrantFiled: September 21, 2015Date of Patent: April 24, 2018Assignee: Cypress Semiconductor CorporationInventors: Harold M. Kutz, Timothy John Williams, Bert S. Sullam, Warren S. Snyder, James H. Shutt, Bruce E. Byrkett, Monte Mar, Eashwar Thiagarajan, Nathan Wayne Kohagen, David G. Wright, Mark E Hastings, Dennis R. Seguine
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Publication number: 20170286344Abstract: An integrated circuit device may include a reconfigurable analog signal switching fabric comprising a plurality of global buses that are selectively connected to external pins by pin connection circuits in response to changeable analog routing data, and a plurality of local buses that are selectively connected to analog blocks and/or global buses by routing connection circuits in response to the analog routing data; and at least one processor circuit that executes predetermined operations in response to instruction data.Type: ApplicationFiled: March 20, 2017Publication date: October 5, 2017Applicant: Cypress Semiconductor CorporationInventors: Bert S. Sullam, Harold M. Kutz, Timothy John Williams, James H. Shutt, Bruce E. Byrkett, Melany Ann Richmond, Nathan Wayne Kohagen, Mark E. Hastings, Eashwar Thiagarajan, Warren S. Snyder
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Publication number: 20170194963Abstract: A apparatus, having a processing system and an input buffer coupled with both the processing system and one of two IO pads, and a reference buffer coupled to both the input buffer and the second of the IO pads such that the reference generator controls the input threshold of the input buffer in response to an analog voltage received from an external circuit on the second of the IO pads.Type: ApplicationFiled: December 5, 2016Publication date: July 6, 2017Inventors: Timothy John Williams, David G. Wright, Gregory John Verge, Bruce E. Byrkett
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Patent number: 9634667Abstract: An integrated circuit (IC) device can include a plurality of analog blocks, including at least one fixed function analog circuit, and at least one reconfigurable analog circuit block selected from: a continuous time (CT) block comprising a plurality of reconfigurable amplifier circuits and a discrete time block comprising amplifiers with a reconfigurable switch network; an analog multiplexer (MUX) configured to selectively connect any of a plurality of input/outputs (I/Os) of the IC device to the analog blocks, the analog MUX including at least one low noise signal path pair having a lower resistance than other signal paths of the analog MUX; at least one analog routing block reconfigurable to provide signal paths between any of the analog blocks; a digital section comprising digital circuits; and a processor interface coupled to the analog blocks.Type: GrantFiled: March 26, 2015Date of Patent: April 25, 2017Assignee: Cypress Semiconductor CorporationInventors: Eashwar Thiagarajan, Harold M. Kutz, Hans Klein, Jaskarn Singh Johal, Jean-Paul Vanitegem, Kendall V. Castor-Perry, Mark E. Hastings, Amsby D. Richardson, Jr., Anasuya Pai Maroor, Ata Khan, Dennis R. Seguine, Bruce E. Byrkett, Carl Ferdinand Liepold, Hans Van Antwerpen
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Patent number: 9612987Abstract: An integrated circuit device may include a reconfigurable analog signal switching fabric comprising a plurality of global buses that are selectively connected to external pins by pin connection circuits in response to changeable analog routing data, and a plurality of local buses that are selectively connected to analog blocks and/or global buses by routing connection circuits in response to the analog routing data; and at least one processor circuit that executes predetermined operations in response to instruction data.Type: GrantFiled: May 7, 2010Date of Patent: April 4, 2017Assignee: Cypress Semiconductor CorporationInventors: Bert Sullam, Harold Kutz, Timothy Williams, James Shutt, Bruce E. Byrkett, Melany Ann Richmond, Nathan Kohagen, Mark Hastings, Eashwar Thiagarajan, Warren Snyder
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Patent number: 9515659Abstract: A apparatus, having a processing system and an input buffer coupled with both the processing system and one of two IO pads, and a reference buffer coupled to both the input buffer and the second of the IO pads such that the reference generator controls the input threshold of the input buffer in response to an analog voltage received from an external circuit on the second of the IO pads.Type: GrantFiled: April 17, 2015Date of Patent: December 6, 2016Assignee: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Timothy John Williams, David G. Wright, Gregory John Verge, Bruce E. Byrkett
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Publication number: 20160065216Abstract: An integrated circuit (IC) device can include a plurality of analog blocks, including at least one fixed function analog circuit, and at least one reconfigurable analog circuit block selected from: a continuous time (CT) block comprising a plurality of reconfigurable amplifier circuits and a discrete time block comprising amplifiers with a reconfigurable switch network; an analog multiplexer (MUX) configured to selectively connect any of a plurality of input/outputs (I/Os) of the IC device to the analog blocks, the analog MUX including at least one low noise signal path pair having a lower resistance than other signal paths of the analog MUX; at least one analog routing block reconfigurable to provide signal paths between any of the analog blocks; a digital section comprising digital circuits; and a processor interface coupled to the analog blocks.Type: ApplicationFiled: March 26, 2015Publication date: March 3, 2016Inventors: Eashwar Thiagarajan, Harold M. Kutz, Hans Klein, Jaskarn Singh Johal, Jean-Paul Vanitegem, Kendall V. Castor-Perry, Mark E. Hastings, Amsby D. Richardson, JR., Anasuya Pai Maroor, Ata Khan, Dennis R. Seguine, Bruce E. Byrkett, Carl Ferdinand Liepold, Hans Van Antwerpen
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Publication number: 20160006439Abstract: A apparatus, having a processing system and an input buffer coupled with both the processing system and one of two IO pads, and a reference buffer coupled to both the input buffer and the second of the IO pads such that the reference generator controls the input threshold of the input buffer in response to an analog voltage received from an external circuit on the second of the TO pads.Type: ApplicationFiled: April 17, 2015Publication date: January 7, 2016Inventors: Timothy John Williams, David G. Wright, Gregory John Verge, Bruce E. Byrkett
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Patent number: 9143134Abstract: A system and apparatus are described for providing greater flexibility and performance in a mixed-signal array through improved and highly configurable routing, control elements and signal processing capabilities.Type: GrantFiled: June 12, 2013Date of Patent: September 22, 2015Assignee: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Harold M. Kutz, Timothy J. Williams, Bert S. Sullam, Warren S. Snyder, James H. Shutt, Bruce E. Byrkett, Monte Mar, Eashwar Thiagarajan, Nathan Kohagen, David G. Wright, Mark E. Hastings, Dennis Raymond Seguine
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Patent number: 9013209Abstract: A apparatus, having a processing system and an input buffer coupled with both the processing system and one of two IO pads, and a reference buffer coupled to both the input buffer and the second of the IO pads such that the reference generator controls the input threshold of the input buffer in response to an analog voltage received from an external circuit on the second of the IO pads.Type: GrantFiled: October 15, 2013Date of Patent: April 21, 2015Assignee: Cypress Semiconductor CorporationInventors: Timothy John Williams, David G. Wright, Gregory John Verge, Bruce E. Byrkett