Abstract: Embodiments include systems and methods for providing reliable and precise sample alignment across different clock domains. Some embodiments operate in context of microprocessor power management circuits seeking correlated measurements of voltage droop (VD) and phase delay (PD). For example, a rolling code is generated for each of multiple second clock domain sample times (CDSTs). VD and the rolling code are both sampled according to a first clock domain to generate VD samples and corresponding VCode samples for each of multiple first CDSTs. PD can be sampled according to the second clock domain to generate PD samples for each of the second CDSTs, each associated with the rolling code for its second CDST. For any first CDST, the VD sample for the first CDST can be aligned with a PD sample for a coinciding second CDST by identifying matching associated rolling codes.

Abstract: Embodiments include systems and methods for providing reliable and precise sample alignment across different clock domains. Some embodiments operate in context of microprocessor power management circuits seeking correlated measurements of voltage droop (VD) and phase delay (PD). For example, a rolling code is generated for each of multiple second clock domain sample times (CDSTs). VD and the rolling code are both sampled according to a first clock domain to generate VD samples and corresponding VCode samples for each of multiple first CDSTs. PD can be sampled according to the second clock domain to generate PD samples for each of the second CDSTs, each associated with the rolling code for its second CDST. For any first CDST, the VD sample for the first CDST can be aligned with a PD sample for a coinciding second CDST by identifying matching associated rolling codes.

Abstract: Embodiments include systems and methods for providing reliable and precise sample alignment across different clock domains. Some embodiments operate in context of microprocessor power management circuits seeking correlated measurements of voltage droop (VD) and phase delay (PD). For example, a rolling code is generated for each of multiple second clock domain sample times (CDSTs). VD and the rolling code are both sampled according to a first clock domain to generate VD samples and corresponding VCode samples for each of multiple first CDSTs. PD can be sampled according to the second clock domain to generate PD samples for each of the second CDSTs, each associated with the rolling code for its second CDST. For any first CDST, the VD sample for the first CDST can be aligned with a PD sample for a coinciding second CDST by identifying matching associated rolling codes.

Abstract: A method of dynamically switching mapping schemes for cache includes a microprocessor, a first mapping scheme, a second mapping scheme and switching circuitry for switching between the first mapping scheme and the second mapping scheme. The microprocessor is in communication with the cache through the switching circuitry and stores information within the cache using one of the first mapping scheme and second mapping scheme. Also, monitoring circuitry for determining whether one of instructions and load/store operations is using the cache is included. Further, the switching circuitry switches between the first mapping scheme and the second mapping scheme based on which one of instructions and load/store operations is using the cache.

Abstract: A coprocessor coupled to a hardware processor and capable of performing multimedia operations is provided. The coprocessor includes an instruction fetch and decode unit which is coupled to a plurality of execution units including an integer execution unit and a multimedia execution unit. The coprocessor includes a superscalar architecture and each of the execution units includes a plurality of pipelined stages. Accordingly, the multimedia execution unit has several integer execution units which can be executed in parallel for improved multimedia performance. A visible register set is coupled to the integer execution unit for receiving operands to initialize operation of the coprocessor. Further, a first register file is coupled to the multimedia execution unit and a second register file is coupled to the integer execution unit. A memory bus coupled to memory and the integer execution unit is used for accessing data and multimedia applications in memory as indicated by values in the visible register set.

Abstract: A computer processor complex including a hardware processor coupled to a multimedia coprocessor is provided. This computer processor complex is capable of separately processing a stream of non-multimedia instructions in addition to a stream of multimedia instructions such as are used in MPEG audio and video. The computer processor complex includes a visible register set including registers for a program counter and a data pointer. The program counter is used to hold the address in memory where the multimedia instructions are located and the data pointer indicates where the data, corresponding to these multimedia instructions, is located in memory. A hardware processor is coupled to a first bidirectional port on the visible register set and a multimedia coprocessor is coupled to a second bidirectional port on the visible register set. The bidirectional ports allow the hardware processor and the coprocessor to exchange data and status information typically using an interrupt based communication mechanism.

Abstract: A "slow" signal is not sent across chip to be combined with combinatorial logic, but rather, the logic with which it would be combined is partitioned such that there are two outputs, one if the "slow" signal would be true and a second if the "slow" signal would be false. Both of these outputs are then provided to a multiplexer. The original "slow" signal selects the correct signal, thus saving the interconnect time delay. The concepts also apply to combinations of multiple "slow" signals.

Abstract: A central processing unit is connected to an external memory including system memory and an external cache. The central processing unit includes a First-In-First-Out (FIFO) load buffer configured to generate an access to the external memory in response to a data prefetch command. The access to external memory has an associated data load latency period as data is moved from the system memory into the external cache. Instead of requiring the access to external memory to be completed before another FIFO load buffer address is processed, as is typically required in a FIFO load buffer configuration, the FIFO load buffer responds to the data prefetch command by processing additional stored addresses during the data load latency period.

Abstract: A microprocessor stepper motor drive uses a single acceleration/deceleration profile regardless of the final velocity of the device being driven. A first down counter stores the desired final velocity from a microprocessor. An acceleration/deceleration profile is stored in a storage device and added to the desired final velocity to produce a smooth velocity profile.

Abstract: Apparatus for defining a bank of sequential windows from a raster-scanned image of a document for storage in a data base. In addition, the apparatus includes a look-up table for each window wherein the bit pattern of the window is used to determine the correction factor which is applied to the next window as the "new" bit from a set of patterns and correction factors derived from well known algorithms developed to minimize the amount of data needed to electronically recreate a given document. The apparatus also includes storage devices to permit the application of the algorithm in overlapping pieces over the face of the document.

Abstract: A method and apparatus for removing undesirable dots and voids which are smaller than the user defined smallest data item of a bit-map image of a picture being scanned by a picture coding system. The bit-map is delayed as it is being generated to form a series of tessellations or windows of data of selected sizes. The windows are propagated through a series of neighborhood-logic elements which with the output data level of the outer ring of neighborhood-logic elements which define the window being examined to determine if those data levels are all of the same sense. If they are all of the same sense, then all of the neighborhood-logic elements which define the interior of the window are set or cleared so that the output data levels of all of the neighborhood-logic elements which define the window are of the same sense.