Abstract: A SAR converter having enhanced performance by virtue of effectively pre-loading the SAR's most significant bits with a value that makes the associated DAC output almost equal to the signal to be converted. A normal SAR conversion is then completed with the SAR bits that have not been pre-loaded. The value used to pre-load the most significant bits of the SAR is preferably obtained from a low-resolution, high-speed converter, such as a flash. The range of DAC bits used in the normal SAR part of the conversion may be increased such that errors up to a certain magnitude in the high-speed converter can be corrected. A method for performing an enhanced SAR conversion is also described.

Abstract: A multi-stage, low-offset, fast-recovery, comparator system and method for: reducing the input offset voltage of the zeroing amplifier by a factor essentially equal to gain of the zeroing amplifier; reducing the input offset voltage of the combined main and zeroing amplifiers by a factor essentially equal to the product of the gains of the main and zeroing amplifiers; and amplifying the input signal to the amplification stage in accordance with the gain of the main amplifier to generate an amplified high-resolution signal.

Abstract: Quasi-differential successive-approximation methods and structures are provided for converting analog signals into corresponding digital signals. These methods and structures realize the signal-to-noise improvements of fully-differential SAR ADCs and the calibration accuracy improvements of pseudo-differential SAR ADCs. Structures of the invention operate in a fully-differential mode to establish more-significant bits of the corresponding digital signals and in a pseudo-differential mode to establish the less-significant bits.