Patents by Inventor Bruce G. Armstrong
Bruce G. Armstrong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11668752Abstract: Implementations of ground fault circuit interrupter (GFCI) self-test circuits may include: a current transformer coupled to a controller, a silicon controlled rectifier (SCR) test loop coupled to the controller, a ground fault test loop coupled to the controller, and a solenoid coupled to the controller. The SCR test loop may be configured to conduct an SCR self-test during a first half wave portion of a phase and the ground fault test loop may be configured to conduct a ground fault self-test during a second half wave portion of a phase. An SCR may be configured to activate the solenoid to deny power to a load upon one of the SCR self-test or the ground fault self-test being identified as failing.Type: GrantFiled: March 1, 2022Date of Patent: June 6, 2023Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Bruce G. Armstrong, Rishi Pratap Singh, Sanath Kumar Kondur Surya Kumar, Riley Beck
-
Publication number: 20220268840Abstract: Implementations of ground fault circuit interrupter (GFCI) self-test circuits may include: a current transformer coupled to a controller, a silicon controlled rectifier (SCR) test loop coupled to the controller, a ground fault test loop coupled to the controller, and a solenoid coupled to the controller. The SCR test loop may be configured to conduct an SCR self-test during a first half wave portion of a phase and the ground fault test loop may be configured to conduct a ground fault self-test during a second half wave portion of a phase. An SCR may be configured to activate the solenoid to deny power to a load upon one of the SCR self-test or the ground fault self-test being identified as failing.Type: ApplicationFiled: March 1, 2022Publication date: August 25, 2022Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Bruce G. ARMSTRONG, Rishi Pratap SINGH, Sanath Kumar KONDUR SURYA KUMAR, Riley BECK
-
Patent number: 11300617Abstract: Implementations of ground fault circuit interrupter (GFCI) self-test circuits may include: a current transformer coupled to a controller, a silicon controlled rectifier (SCR) test loop coupled to the controller, a ground fault test loop coupled to the controller, and a solenoid coupled to the controller. The SCR test loop may be configured to conduct an SCR self-test during a first half wave portion of a phase and the ground fault test loop may be configured to conduct a ground fault self-test during a second half wave portion of a phase. An SCR may be configured to activate the solenoid to deny power to a load upon one of the SCR self-test or the ground fault self-test being identified as failing.Type: GrantFiled: July 1, 2019Date of Patent: April 12, 2022Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Bruce G. Armstrong, Rishi Pratap Singh, Sanath Kumar Kondur Surya Kumar, Riley Beck
-
Publication number: 20200041567Abstract: Implementations of ground fault circuit interrupter (GFCI) self-test circuits may include: a current transformer coupled to a controller, a silicon controlled rectifier (SCR) test loop coupled to the controller, a ground fault test loop coupled to the controller, and a solenoid coupled to the controller. The SCR test loop may be configured to conduct an SCR self-test during a first half wave portion of a phase and the ground fault test loop may be configured to conduct a ground fault self-test during a second half wave portion of a phase. An SCR may be configured to activate the solenoid to deny power to a load upon one of the SCR self-test or the ground fault self-test being identified as failing.Type: ApplicationFiled: July 1, 2019Publication date: February 6, 2020Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Bruce G. ARMSTRONG, Rishi Pratap SINGH, Sanath Kumar KONDUR SURYA KUMAR, Riley BECK
-
Patent number: 8085516Abstract: A ground fault circuit interrupter (GFCI) includes a GFCI controller configured to detect for ground faults and to periodically perform a self test. The self test may be performed during a positive half cycle of an AC line voltage coupled to a load by the GFCI. The self test may include testing of a critical component of the GFCI without opening load contacts coupling the AC line voltage to the load. The self test may further include testing of monitoring coils in the GFCI.Type: GrantFiled: July 11, 2008Date of Patent: December 27, 2011Assignee: Fairchild Semiconductor CorporationInventor: Bruce G. Armstrong
-
Patent number: 5926412Abstract: Architectures for a ferroelectric memory which avoids the half select phenomenon and the problems associated with destructive readout. Non-destructive readout is provided by measuring current through the ferroelectric memory as a measure of its resistance. Information is stored in the ferroelectric memory element by altering its resistance through a polarizing voltage. The half select phenomenon is avoided by using isolation techniques. In various embodiments, zener diodes or bipolar junction transistors are used for isolation.Type: GrantFiled: April 2, 1992Date of Patent: July 20, 1999Assignee: Raytheon CompanyInventors: Joseph T. Evans, Jr., Jeff A. Bullington, Stephen E. Bernacki, Bruce G. Armstrong
-
Patent number: 5796303Abstract: An audio amplifier that does not exhibit a "pop" during a change-of-state such as being turned on. The popless amplifier includes an operational amplifier to power a speaker, a circuit to prevent the application of an output voltage from the operational amplifier to the speaker for a selectable period of time and a circuit to charge the output of the operational amplifier to a selectable mid-rail voltage during the time a voltage from the operational amplifier is prevented from reaching the speaker.Type: GrantFiled: June 26, 1996Date of Patent: August 18, 1998Inventors: Charles L. Vinn, Bruce G. Armstrong
-
Patent number: 5166901Abstract: A memory cell comprising a memory region of amorphous silicon, such memory region having a first state of substantial electrical nonconductivity programmable to a second state of substantial electrical conductivity in response to an electrical programming signal applied thereto. The memory region is disposed over a metal Schottky contact, such as platinum-silicide (PtSi), formed in a support body. A first barrier layer comprising a refractory metal such as titanium-tungsten (TiW) is disposed between the memory region and Schottky contact. A first input terminal comprising a metal strip conductor, such as aluminum, is disposed over the memory region, with a second refractory metal barrier layer being disposed between the memory region and metal strip conductor. A second input terminal is disposed within the support body.Type: GrantFiled: February 26, 1991Date of Patent: November 24, 1992Assignee: Raytheon CompanyInventors: Gerard J. Shaw, Jok Y. Go, Jay H. Chun, Bruce G. Armstrong, Jerry W. Drake
-
Patent number: 4686651Abstract: A memory integrated circuit component comprises: a memory; addressing circuitry for the memory; and, power switch circuit, programmable to either: (a) electrically couple or decouple the addressing circuitry and a power supply selectively in accordance with an enable signal; or, (b) maintain the addressing circuitry electrically coupled to the power supply independent of the enable signal.With such arrangement, an integrated circuit component manufacturer avoids having to produce two separate types of non-volatile integrated circuit memories (i.e., a power switched component and a non-power switched component), but rather such manufacturer is able to fabricate a common non-volatile integrated circuit memory component which may be programmed after fabrication by either the user or the manufacturer as either a non-power switched memory component or a power switched memory component.Type: GrantFiled: November 15, 1984Date of Patent: August 11, 1987Assignee: Raytheon CompanyInventors: Bruce G. Armstrong, Fabio Principi
-
Patent number: 4593383Abstract: An integrated circuit memory is disclosed having a power switch circuit which, in response to an enable signal, initially addresses a plurality of rows of memory elements during an initial pre-enable condition and which subsequently places the memory in the full enable condition to allow the address signal to address only a selected one of the plurality of memory elements. During a standby mode the rows of conductors coupled to the rows of memory elements are at a relatively "high" voltage potential charging the large capacitance between the rows of conductors and a grounded substrate on which such conductors are formed. To address a particular row conductor and hence the memory elements coupled thereto during the enable mode, such row conductor must be coupled to ground potential.Type: GrantFiled: November 2, 1983Date of Patent: June 3, 1986Assignee: Raytheon CompanyInventors: Bruce G. Armstrong, Fabio Principi, John G. Marcellino
-
Patent number: 4561070Abstract: An integrated circuit memory is provided wherein an array of memory elements is addressed by a decoder circuit responding to an address signal. The decoder circuit includes a plurality of sections, each one thereof being used to address a different section of the array. A decoder section selector is provided which, in response to the addressing signal, determines the section of the array being addressed and electrically couples the one of the plurality of decoder circuit sections which is coupled to such addressed array section to a power source while electrically decoupling the remaining section of the decoder circuit from such power source. With such arrangement, only a portion of the decoder circuit is electrically coupled to the power source when addressing the array thereby reducing the power consumption of the integrated circuit memory.Type: GrantFiled: July 1, 1983Date of Patent: December 24, 1985Assignee: Raytheon CompanyInventor: Bruce G. Armstrong
-
Patent number: 4385368Abstract: A programmable read-only memory (PROM) circuit is provided wherein each one of a plurality of fusible links is coupled between a different row and column conductor of a matrix of row and column conductors and wherein each one of the row conductors is coupled to a corresponding one of a plurality of row driver circuits, each one having an output transistor connected to the corresponding one of the row conductors. Switch means are provided for feeding a first level of base current to the output transistors during the programming mode and for feeding a second, lower level of base current to such output transistors during the read mode.Type: GrantFiled: November 24, 1980Date of Patent: May 24, 1983Assignee: Raytheon CompanyInventors: Fabio Principi, Bruce G. Armstrong