Abstract: A phase error detection circuit apparatus and method for detecting phase misalignment between first clock signals operating in a slow time domain and second clock signals operating in a fast time domain. A frequency divider and shift register are clocked in the slow time domain to sequentially sample all possible alignments of the first clock signals. A second shift register is clocked in the fast time domain and operates responsive to the output of the frequency divider and shift register to generate a phase alignment error signal when the phase alignment is incorrect or the frequency divider is not switching in a correct cycle. Error detection logic clocked in the slow time domain samples and optionally masks the phase error signal. State machine logic may be provided to generate an output error signal when each possible phase alignment results in a phase alignment error signal.

Abstract: In a system of digital chips, the time delay in all clock trees is equalized by equalizing the delay through each level of all trees. The level delays are equalized by adjusting the capacitance of terminators in each net at each level, and/or by adjusting the performance (power) of each driver at each level. Where the capacitance of a net is too low to be compensated by a driver, a capacitive terminator is selectively added to that net.

Abstract: In a system of digital chips, the time delay in all clock trees is equalized by equalizing the delay through each level of all trees. The level delays are equalized by adjusting the capacitance of terminators in each net at each level, and/or by adjusting the performance (power) of each driver at each level. Where the capacitance of a net is too low to be compensated by a driver, a capacitive terminator is selectively added to that net.

Abstract: A performance-sensing element (PSE) circuit detects the actual speed of other circuits on the same chip by launching a pulse into a tapped cascade of circuits on the chip, then detecting how far the pulse has progressed after a known interval. Control signals indicating circuit speed can stabilize parameters of the other circuits, such as rate of change of current (di/dt) in driver circuits, absolute delay of clock signals from one chip to another, and relative delay of multiple clock signals within the chip.