Abstract: A method and apparatus for modeling using a hardware-software software co-verification environment is provided. An instruction set simulator is coupled to a simulator circuit to determine if the hardware design is correct. Specifically, the instruction set simulator acts as a “master” to the simulator circuit, thus providing a faster simulation environment. The simulator circuit contains a bus functional model, a hardware model, transfer memory, and the hardware design to be tested. The hardware model is designed to emulate a micro-controller. By disabling a processor within the hardware model, the speed of the simulation is restricted only by the speed of the instruction set simulator or the hardware design. Furthermore, the hardware design may be uncoupled from the simulator circuit in order to initialize the operating system.

Abstract: An apparatus and method for preparing a disk for use in a disk array, the disk array including an input/output control processor, the disk including sectors, the sectors including a data area and a metadata area, the method comprising defining a range of sectors to prepare for use in the disk array, sending a command to the disk from the input/output control processor, the command instructing the disk to write a block of initial state data to each sector in a group of sectors on the disk, the group of sectors on the disk located within the range of sectors on the disk, and writing the block of initial state data to each of the sectors on the disk. The block of initial state data comprises a bit stream of data for writing to the data area and the metadata area of each sector.