Abstract: Gate all around semiconductor devices, such as nanowire or nanoribbon devices, are described that include a low dielectric constant (“low-k”) material disposed between a first nanowire closest to the substrate and the substrate. This configuration enables gate control over all surfaces of the nanowires in a channel region of a semiconductor device via the high-k dielectric material, while also preventing leakage current from the first nanowire into the substrate.

Abstract: Gate-all-around integrated circuit structures fabricated using alternate etch selective material, and the resulting structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is over the vertical arrangement of horizontal nanowires. A pair of dielectric spacers is along sides of the gate stack and over the vertical arrangement of horizontal nanowires. A metal oxide material is between adjacent ones of the vertical arrangement of horizontal nanowires at a location between the pair of dielectric spacers and the sides of the gate stack.

Abstract: A coupled graph database pair for management of a platform is presented. The coupled graph database pair comprises a model graph database managed in a manufacturer environment, an instance graph database managed in a customer environment, and a plurality of relationships between the nodes of the model graph database and the nodes of the instance graph database. The model graph database comprises nodes of assemblies, sub-assemblies, and parts for a designed configuration of a model of the platform. The instance graph database comprises nodes of assemblies, sub-assemblies, and parts for a real-time configuration of the platform.

Abstract: Non-planar integrated circuit structures having mitigated source or drain etch from replacement gate process are described. For example, an integrated circuit structure includes a fin or nanowire. A gate stack is over the fin or nanowire. The gate stack includes a gate dielectric and a gate electrode. A first dielectric spacer is along a first side of the gate stack, and a second dielectric spacer is along a second side of the gate stack. The first and second dielectric spacers are over at least a portion of the fin or nanowire. An insulating material is vertically between and in contact with the portion of the fin or nanowire and the first and second dielectric spacers. A first epitaxial source or drain structure is at the first side of the gate stack, and a second epitaxial source or drain structure is at the second side of the gate stack.

Abstract: An additive manufacturing system includes an additive manufacturing tool configured to receive a plurality of metallic anchoring materials and to supply a plurality of droplets to a part, and a controller configured to independently control the composition, formation, and application of each droplet to the plurality of droplets to the part. The plurality of droplets is configured to build up the part. Each droplet of the plurality of droplets includes at least one metallic anchoring material of the plurality of metallic anchoring materials.

Abstract: A nanowire device includes one or more nanowire having a first end portion, a second end portion, and a body portion between the first end portion and the second end portion. A first conductive structure is in contact with the first end portion and a second conductive structure is in contact with the second end portion. The body portion of the nanowire has a first cross-sectional shape and the first end portion has a second cross-sectional shape different from the first cross-sectional shape. Integrated circuits including the nanowire device and a method of cleaning a semiconductor structure are also disclosed.

Abstract: A transistor structure includes a base and a body over the base. The body comprises a semiconductor material and has a first end portion and a second end portion. A gate structure is wrapped around the body between the first end portion and the second end portion, where the gate structure includes a gate electrode and a dielectric between the gate electrode and the body. A source is in contact with the first end portion and a drain is in contact with the second end portion. A first spacer material is on opposite sides of the gate electrode and above the first end portion. A second spacer material is adjacent the gate structure and under the first end portion of the nanowire body. The second spacer material is below and in contact with a bottom surface of the source and the drain.

Abstract: A method for manufacturing an isolating layer onto a crucible includes the steps as follows: providing a spraying device for the following spraying steps; heating the crucible and measuring the heated crucible to get a first temperature; spraying a slurry on the inner wall of the crucible to form an isolating layer by a spraying unit with a predetermined spraying manner; measuring the isolating layer to get a second temperature; obtaining a value for the difference between the first and second temperatures and judging whether the difference value in a within predetermined difference scope or not, in which the predetermined difference scope is about 6° C.˜12° C.; when the difference value is not in the predetermined difference scope, adjusting the predetermined spraying manner; when the difference value is in the predetermined difference scope, implementing the above spraying steps to the crucible.

Abstract: A crystal growth device includes a crucible and a heater setting. The crucible has a bottom and a top opening. The heater setting surrounds the crucible and is movable relative to the crucible along a top-bottom direction of the crucible and between first and second positions. The heater setting includes a first temperature heating zone and a second temperature heating zone higher in temperature than the first temperature heating zone. The heater setting is in the first position when the crucible is in the second temperature heating zone and in the second position when the crucible is in the first temperature heating zone.

Abstract: A method for manufacturing an isolating layer onto a crucible includes the steps as follows: providing a spraying device for the following spraying steps; heating the crucible and measuring the heated crucible to get a first temperature; spraying a slurry on the inner wall of the crucible to form an isolating layer by a spraying unit with a predetermined spraying manner; measuring the isolating layer to get a second temperature; obtaining a value for the difference between the first and second temperatures and judging whether the difference value in a within predetermined difference scope or not, in which the predetermined difference scope is about 6° C.˜12° C.; when the difference value is not in the predetermined difference scope, adjusting the predetermined spraying manner; when the difference value is in the predetermined difference scope, implementing the above spraying steps to the crucible.

Abstract: In a crystalline silicon formation apparatus, a quick cooling method is applied to the bottom of a crucible to control a growth orientation of a polycrystalline silicon grain, such that the crystal grain forms twin boundary, and the twin boundary is a symmetric grain boundary, and the crystal grain is solidified and grown upward in unidirection to form a complete polycrystalline silicon, such that defects or impurities will not form in the polycrystalline silicon easily.

Abstract: A crystal growth device includes a crucible and a heater setting. The crucible has a bottom and a top opening. The heater setting surrounds the crucible and is movable relative to the crucible along a top-bottom direction of the crucible and between first and second positions. The heater setting includes a first temperature heating zone and a second temperature heating zone higher in temperature than the first temperature heating zone. The heater setting is in the first position when the crucible is in the second temperature heating zone and in the second position when the crucible is in the first temperature heating zone.

Abstract: A method of multi-terminal connection traversing a network address translation (NAT) without third party interfacing is provided, which is applicable to existing network communication protocols. The method is mainly used to realize connection of a user end having a NAT or a firewall with a third party, and enable the user end to form direct network interconnection with other user ends through a multi-terminal network connection system without additionally opening a network connection port for the NAT or firewall. Moreover, the method enables a user of the user end to additionally load Internet application programs, such as Voice over Internet Protocol (VoIP) and video conference, on the multi-terminal network connection system based on demands of the user or for work.

Abstract: In a crystalline silicon formation apparatus, a quick cooling method is applied to the bottom of a crucible to control a growth orientation of a polycrystalline silicon grain, such that the crystal grain forms twin boundary, and the twin boundary is a symmetric grain boundary, and the crystal grain is solidified and grown upward in unidirection to form a complete polycrystalline silicon, such that defects or impurities will not form in the polycrystalline silicon easily.

Abstract: The present invention provides a program sharer software that uses technology including storage systems on servers and data access redirection to enable frequently used software (such as document editing software, program development tools, drawing software, ERP software, CAD/CAM software mail software, and so on,) to be executed on client terminals, when, in fact, the software is installed on centralized management software servers. The data access redirection technology in the Windows OS is separated into file redirection, registry redirection, local facilities usage and font installation.

Abstract: A gain calibration device and method for differential push-pull (DPP) tracking error signals in an optical storage system is provided. The gain calibration method processes the synthesized gain (SPPG) of the sub beam in the DPP tracking error signal components with respect to the main beam. The calibration theorem resides in controlling the objective lens of the pick-up head to form a lens-shift or controlling the tilt of the objective lens relative to the optical disc to make the synthesized DPP tracking error signals generate a correspondingly signal variation owing to the optical path deviation. The synthesized gain is calibrated to make the signal variation a minimum value, and the calibrated synthesized gain is the optimum value.

Abstract: A gain calibration device and method for differential push-pull (DPP) tracking error signals in an optical storage system is provided. The gain calibration method processes the synthesized gain (SPPG) of the sub beam in the DPP tracking error signal components with respect to the main beam. The calibration theorem resides in controlling the objective lens of the pick-up head to form a lens-shift or controlling the tilt of the objective lens relative to the optical disc to make the synthesized DPP tracking error signals generate a correspondingly signal variation owing to the optical path deviation. The synthesized gain is calibrated to make the signal variation a minimum value, and the calibrated synthesized gain is the optimum value.