Patents by Inventor Bruce L. Pickelsimer

Bruce L. Pickelsimer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6434217
    Abstract: A system and method are presented for determining the thickness and elemental composition of a layer within a measurement sample in an easy and inexpensive manner. An embodiment of the method includes impinging an incident x-ray beam into an exposed surface of a measurement sample containing one or more layers. The incident x-ray beam passes through the sample and may refract depending on the composition of the layers to produce a transmitted x-ray beam. The intensity and the angle of refraction of the transmitted x-ray beam may then be measured. These measurements may be compared to the results of a calibration sample that has been prepared with a known thickness and composition relative to the layer characteristics of the sample. The intensity of the transmitted x-ray beam is a function of the thickness of the layer; while the angle of refraction is a function of the elemental composition of the layer.
    Type: Grant
    Filed: October 10, 2000
    Date of Patent: August 13, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Bruce L. Pickelsimer, Tim Z. Hossain
  • Patent number: 5882990
    Abstract: A method of manufacturing a silicon substrate which optimizes extrinsic gettering during semiconductor fabrication is provided in which phosphorous ions are diffused into the backside surface of a silicon substrate during wafer slice manufacture. Forming gettering sites at the backside surface prior to gate polysilicon deposition, extrinsic gettering is optimized. Initially, both the frontside and backside surfaces of a silicon substrate are subjected to dopant materials. Thereafter, at least one thin film is formed on both the frontside and backside surfaces. The thin films are then removed from the frontside surface along with a layer of the silicon substrate immediately below the frontside surface to a depth of about 10.0 .mu.m. The final polishing step of a typical silicon wafer manufacturing process removes a layer of silicon to a depth of about 10.0 .mu.
    Type: Grant
    Filed: January 7, 1998
    Date of Patent: March 16, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Damon K. DeBusk, Bruce L. Pickelsimer
  • Patent number: 5789308
    Abstract: A method of manufacturing a silicon substrate which optimizes extrinsic gettering during semiconductor fabrication is provided in which phosphorous ions are diffused into the backside surface of a silicon substrate during wafer slice manufacture. Forming gettering sites at the backside surface prior to gate polysilicon deposition, extrinsic gettering is optimized. Initially, both the frontside and backside surfaces of a silicon substrate are subjected to dopant materials. Thereafter, at least one thin film is formed on both the frontside and backside surfaces. The thin films are then removed from the frontside surface along with a layer of the silicon substrate immediately below the frontside surface to a depth of about 10.0 .mu.m. The final polishing step of a typical silicon wafer manufacturing process removes a layer of silicon to a depth of about 10.0 .mu.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: August 4, 1998
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Damon K. DeBusk, Bruce L. Pickelsimer
  • Patent number: 5739067
    Abstract: A method for the formation of active devices upon and within exposed surfaces of both sides of a silicon wafer is presented. A dual-sided silicon wafer is provided having a first surface and an opposed second surface prepared similarly to achieve surfaces suitable for fabricating semiconductor devices. The method advantageously integrates the ability to preform wafer processing operations on both exposed surfaces separately or simultaneously. Wafer processing operations are layering, patterning, doping, and heat treatment. The processing sequence is complete when a doped region and a patterened interconnect line electrically coupled thereto (i.e., minimal integrated circuits) are formed upon and within both surfaces of the dual-sided silicon wafer. A wafer handling system and processing station for dual-sided silicon wafers are described. In addition, a technique of applying a protective layer over one surface of a dual-sided silicon wafer is also described.
    Type: Grant
    Filed: December 7, 1995
    Date of Patent: April 14, 1998
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Damon K. DeBusk, Bruce L. Pickelsimer