Abstract: A processor system includes an I/O bus to host bridge in which I/O address translation elements are shared across multiple I/O bus bridges. A TCE manager is provided for retaining in cache a TCE entry associated with a discarded channel for association with a new channel responsive to a subsequent read request for a memory page referenced by the TCE entry.

Abstract: A clustered computer system, bridge device and method include support for an atomic ownership change operation that ensures orderly and reliable ownership management of an input/output (I/O) bridge device. A lock indicator is associated with a bridge device, and is used to indicate a “locked” or “unlocked” status of the bridge device. Whenever the lock indicator indicates that the bridge device is unlocked, an atomic operation such as a read request to a lock indicator register is utilized to both set the indicator to indicate a locked status for the bridge device, and to associate the bridge device with a source node that initiated the atomic operation. In connection with the lock indicator, write access to one or more configuration parameter registers is controlled such that only the node that is associated with the bridge device is permitted to update such configuration parameter registers.

Abstract: A method, computer program product, and data processing system for sharing memory protection tables and address translation tables among multiple Host Channel Adapters are disclosed. The protection and address translation tables for a shared memory region are written in memory of the host. The Host Channel Adapters are registered with the memory region so that each adapter stores an address pointer to the tables. In this way, the tables need not be duplicated for each adapter.

Abstract: A method, system, and product in a data processing system are disclosed for testing a switched area network device having a standardized serial fabric interconnect and that includes logic modules. The device includes test mode logic. A test command is received within the test mode logic via the standardized serial fabric interconnect from an external tester. The test command is then executed by the test mode logic, and a result of the test is then transmitted to the tester via the standardized serial fabric interconnect.

Abstract: A method, program and system for associating memory windows with memory regions in an infiniband data storage system are provided. The invention comprises registering a Memory Region, wherein the Memory Region is a set of virtually contiguous memory addresses defined by a virtual address and length. The system then establishes and maintains a Window Reference Count (WRC) for the Memory Region, which tracks the number of Memory Windows which are bound to the Memory Region. When the system binds a Memory Window to the Memory Region, the value of the WRC is incremented. When a Memory Window is unbound from the Memory Region, the value of the WRC is decremented. If no Memory Windows are bound to the Memory Region, the value of the WRC is zero. The Memory Region is not deregistered unless the value of the WRC equals zero.

Abstract: A method, system, and product in a data processing system are disclosed for managing data transmitted from a first end node to a second end node included in the data processing system. A logical connection is established between the first end node and the second end node prior to transmitting data between the end nodes. An instance number is associated with this particular logical connection. The instance number is included in each packet transmitted between the end nodes while this logical connection remains established. The instance number remains constant during this logical connection. The instance number is altered, such as by incrementing it, each time a logical connection between these end nodes is reestablished. Thus, each packet is associated with a particular instance of the logical connection. When a packet is received, the instance number included in the packet may be used to determine whether the packet is a stale packet transmitted during a previous logical connection between these end nodes.

Abstract: A method, system and program for controlling access to memory areas within a computer are provided. The invention comprises placing a first Bind Work Queue Element (WQE) at the head of a work queue, wherein the first Bind WQE defines parameters associated with a first Memory Window. A set of Work Requests is then placed on the work queue, behind the first Bind WQE wherein the work requests invoke operations that access the first Memory Window. A second Bind WQE is then placed on the work queue, behind the first set of Work Requests. This second Bind WQE defines parameters associated with a second Memory Window. A second set of Work Requests is placed on the work queue behind the second Bind WQE and invoke operations that access the second memory window. The Memory Windows can be associated with a common Memory Region and have different addresses and lengths or different access rights. In another embodiment, the first and second Memory Windows can be associated with different Memory Regions.

Abstract: A method, system and program for controlling access to computer memory are provided. The present invention comprises receiving a work request from a user, wherein the work request comprises an index portion and a protection portion. The index portion of the work request is used to locate an element in an address translation and protection table. The protection portion of the work request is then compared with a protection key in the table element, and access to memory is granted only if the protection portion and protection key match.

Abstract: A method, computer program product, and data processing system for sharing memory protection tables and address translation tables among multiple Host Channel Adapters are disclosed. The protection and address translation tables for a shared memory region are written in memory of the host. The Host Channel Adapters are registered with the memory region so that each adapter stores an address pointer to the tables. In this way, the tables need not be duplicated for each adapter.

Abstract: An ordering mechanism, ordering method and computer program product are provided for implementing PCI local bus (PCI) peer to peer functions. When a read command is received, checking for available resource is performed. Responsive to not identifying available resource, a retry read command is sent. Responsive to sending the read command; checking for the retry read received command is provided. Responsive to identifying the retry read received command, the read command is resent.

Abstract: An apparatus and method for implementing mulitcast in system area network channel adapters are provided. With the apparatus and method, a multicast packet is received in a channel adapter of an end node. The channel adapter determines which local queue pairs are party of the multicast group identified by a destination local identifier in the multicast data packet. Based on this determination, the channel adapter replicates the data packet and delivers a copy of the data packet to each local queue pair that is part of the multicast group.

Abstract: A method, program and system for associating memory windows with memory regions in an infiniband data storage system are provided. The invention comprises registering a Memory Region, wherein the Memory Region is a set of virtually contiguous memory addresses defined by a virtual address and length. The system then establishes and maintains a Window Reference Count (WRC) for the Memory Region, which tracks the number of Memory Windows which are bound to the Memory Region. When the system binds a Memory Window to the Memory Region, the value of the WRC is incremented. When a Memory Window is unbound from the Memory Region, the value of the WRC is decremented. If no Memory Windows are bound to the Memory Region, the value of the WRC is zero. The Memory Region is not deregistered unless the value of the WRC equals zero.

Abstract: A circuit arrangement, node, clustered computer system, and method incorporate a primitive communication mechanism for use in exchanging data between adjacent nodes coupled via a point-to-point network. A plurality of network ports are used to couple a node to other nodes in the clustered computer system over point-to-point network interconnects, and a plurality of communication registers are associated with each of the network ports for the purpose of storing data received through their associated network ports. A node desiring to communicate information to another node receives a port identifier from the other node that identifies the network port on the other node through which the pair of nodes are coupled. The port identifier is then used by the node to communicate data to the other node through the use of one or more write operations directed to the communication register on the other node that is associated with the network port identified by the port identifier.

Abstract: A clustered computer system, bridge device and method include support for an atomic ownership change operation that ensures orderly and reliable ownership management of an input/output (I/O) bridge device. A lock indicator is associated with a bridge device, and is used to indicate a “locked” or “unlocked” status of the bridge device. Whenever the lock indicator indicates that the bridge device is unlocked, an atomic operation such as a read request to a lock indicator register is utilized to both set the indicator to indicate a locked status for the bridge device, and to associate the bridge device with a source node that initiated the atomic operation. In connection with the lock indicator, write access to one or more configuration parameter registers is controlled such that only the node that is associated with the bridge device is permitted to update such configuration parameter registers.

Abstract: A method, system and program for controlling access to memory areas within a computer are provided. The invention comprises placing a first Bind Work Queue Element (WQE) at the head of a work queue, wherein the first Bind WQE defines parameters associated with a first Memory Window. A set of Work Requests is then placed on the work queue, behind the first Bind WQE wherein the work requests invoke operations that access the first Memory Window. A second Bind WQE is then placed on the work queue, behind the first set of Work Requests. This second Bind WQE defines parameters associated with a second Memory Window. A second set of Work Requests is placed on the work queue behind the second Bind WQE and invoke operations that access the second memory window. The Memory Windows can be associated with a common Memory Region and have different addresses and lengths or different access rights. In another embodiment, the first and second Memory Windows can be associated with different Memory Regions.

Abstract: A method, system and program for controlling access to computer memory are provided. The present invention comprises receiving a work request from a user, wherein the work request comprises an index portion and a protection portion. The index portion of the work request is used to locate an element in an address translation and protection table. The protection portion of the work request is then compared with a protection key in the table element, and access to memory is granted only if the protection portion and protection key match.

Abstract: A method and apparatus for accessing a memory. Access rights for a memory operation are verified using a first data structure in response to receiving a request to perform the operation, wherein the request includes a virtual address for the operation. Responsive to access rights being verified for the memory operation, the virtual address translated into a real address using a second data structure.

Abstract: A method, system, and apparatus for processing foreign protocol requests, such as PCI transactions, across a system area network (SAN) utilizing a data packet protocol is provided while maintaining the other SAN traffic. In one embodiment, a HCA receives a request for a load or store operation from a processor to an I/O adapter using a protocol which is foreign to the system area network, such as a PCI bus protocol. The HCA encapsulates the request into a data packet and places appropriate headers and trailers in the data packet to ensure that the data packet is delivered across the SAN fabric to an appropriate TCA to which the requested I/O adapter is connected. The TCA receives the data packet, determines that it contains a foreign protocol request, and decodes the data packet to obtain the foreign protocol request. The foreign protocol request is then transmitted to the appropriate I/O adapter.

Abstract: A computing system includes a processing system, at least a first register, and a control system. The processing system generates a first instruction set and a first address for storing a first completion status for the first instruction set. The first register receives the first address from the processing system. The control system communicates the first instruction set received from the processing system to an external device. The control system receives the first completion status from the external device, accesses the first register to determine the first address for the first instruction set, and stores the first completion status in the determined first address.

Abstract: A peripheral interconnect for a computer system comprising a bridge, a peripheral bus, and a peripheral device, wherein at least one of these components is adapted to selectively operate in either a high performance mode or a low performance mode, the high performance mode using a first operating speed and a first protocol, and the low performance mode using a second operating speed which is lower than said first operating speed, and a second protocol which is different from the first protocol. The disclosed embodiment provides a high performance mode with a 100 MHz speed and a protocol that disallows pacing, and a low performance mode that uses a 66 MHz or 33 MHz speed and a standard PCI protocol that allows pacing. The high performance operating speed can be twice the low performance operating speed, by doubling the clock frequency and clocking data on only one clock edge, or by clocking data on both a rising edge and a falling edge of a clock signal while operating at the lower clock frequency.