Patents by Inventor Bruce M. Fleischer

Bruce M. Fleischer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Soft error detection for latches
    Patent number: 8188761
    Abstract: A system and method for soft error detection in digital ICs is disclosed. The system includes an observing circuit coupled to a latch, which circuit is capable of a response upon a state change of the latch. The system further includes synchronized clocking provided to the latch and to the observing circuit. For the latch, the clocking defines a window in time during which the latch is prevented from receiving data, and in a synchronized manner the clocking is enabling a response in the observing circuit. The clocking is synchronized in such a manner that the circuit is enabled for its response only inside the window when the latch is prevented from receiving data. The system may also have additional circuits that are respectively coupled to latches, with each the additional circuit and its respective latch receiving the synchronized clocking Responses of a plurality of circuits may be coupled in a configuration corresponding to a logical OR.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: May 29, 2012
    Assignee: International Business Machines Corporation
    Inventors: Bruce M. Fleischer, Michael K. Gschwind
  • Method and system for a wiring-efficient permute unit
    Patent number: 8069195
    Abstract: A method of providing wiring efficiency in a permute unit. Multiple selectors receive input data and shared control signals from multiple register files. The permute unit includes multiple multiplexors (MUXs) coupled to multiple logical AND gates. The multiple logical AND gates are coupled to multiple logical OR gates. The logical AND gates are physically separated from the logical OR gates. The logical AND gates receive input from one or more output data signals from the selectors. The logical OR gates combine the one or more output signals from the logical AND gates and provide output data from the permute unit.
    Type: Grant
    Filed: January 3, 2008
    Date of Patent: November 29, 2011
    Assignee: International Business Machines Corporation
    Inventors: Bruce M. Fleischer, Hung C. Ngo, Jun Sawada
  • SOFT ERROR DETECTION FOR LATCHES
    Publication number: 20110221473
    Abstract: A system and method for soft error detection in digital ICs is disclosed. The system includes an observing circuit coupled to a latch, which circuit is capable of a response upon a state change of the latch. The system further includes synchronized clocking provided to the latch and to the observing circuit. For the latch, the clocking defines a window in time during which the latch is prevented from receiving data, and in a synchronized manner the clocking is enabling a response in the observing circuit. The clocking is synchronized in such a manner that the circuit is enabled for its response only inside the window when the latch is prevented from receiving data. The system may also have additional circuits that are respectively coupled to latches, with each the additional circuit and its respective latch receiving the synchronized clocking Responses of a plurality of circuits may be coupled in a configuration corresponding to a logical OR.
    Type: Application
    Filed: February 14, 2011
    Publication date: September 15, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce M. Fleischer, Michael K. Gschwind
  • MULTI-PETASCALE HIGHLY EFFICIENT PARALLEL SUPERCOMPUTER
    Publication number: 20110219208
    Abstract: A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC).
    Type: Application
    Filed: January 10, 2011
    Publication date: September 8, 2011
    Applicant: International Business Machines Corporation
    Inventors: Sameh Asaad, Ralph E. Bellofatto, Michael A. Blocksome, Matthias A. Blumrich, Peter Boyle, Jose R. Brunheroto, Dong Chen, Chen-Yong Cher, George L. Chiu, Norman Christ, Paul W. Coteus, Kristan D. Davis, Gabor J. Dozsa, Alexandre E. Eichenberger, Noel A. Eisley, Matthew R. Ellavsky, Kahn C. Evans, Bruce M. Fleischer, Thomas W. Fox, Alan Gara, Mark E. Giampapa, Thomas M. Gooding, Michael K. Gschwind, John A. Gunnels, Shawn A. Hall, Rudolf A. Haring, Philip Heidelberger, Todd A. Inglett, Brant L. Knudson, Gerard V. Kopcsay, Sameer Kumar, Amith R. Mamidala, James A. Marcella, Mark G. Megerian, Douglas R. Miller, Samuel J. Miller, Adam J. Muff, Michael B. Mundy, John K. O'Brien, Kathryn M. O'Brien, Martin Ohmacht, Jeffrey J. Parker, Ruth J. Poole, Joseph D. Ratterman, Valentina Salapura, David L. Satterfield, Robert M. Senger, Brian Smith, Burkhard Steinmacher-Burow, William M. Stockdell, Craig B. Stunkel, Krishnan Sugavanam, Yutaka Sugawara, Todd E. Takken, Barry M. Trager, James L. Van Oosten, Charles D. Wait, Robert E. Walkup, Alfred T. Watson, Robert W. Wisniewski, Peng Wu
  • Soft error detection for latches
    Patent number: 7977965
    Abstract: A system and method for soft error detection in digital ICs is disclosed. The system includes an observing circuit coupled to a latch, which circuit is capable of a response upon a state change of the latch. The system further includes synchronized clocking provided to the latch and to the observing circuit. For the latch, the clocking defines a window in time during which the latch is prevented from receiving data, and in a synchronized manner the clocking is enabling a response in the observing circuit. The clocking is synchronized in such a manner that the circuit is enabled for its response only inside the window when the latch is prevented from receiving data. The system may also have additional circuits that are respectively coupled to latches, with each the additional circuit and its respective latch receiving the synchronized clocking. Responses of a plurality of circuits may be coupled in a configuration corresponding to a logical OR.
    Type: Grant
    Filed: March 12, 2010
    Date of Patent: July 12, 2011
    Assignee: International Business Machines Corporation
    Inventors: Bruce M. Fleischer, Michael K. Gschwind
  • Aligning precision converted vector data using mask indicating offset relative to element boundary corresponding to precision type
    Patent number: 7865693
    Abstract: Mechanisms for aligning enhanced precision vectors based on reduced precision data values are provided. At least one data value, having a first precision type, is received for storing in a vector register. The vector register stores data as a vector having a plurality of vector elements. The first precision type is modified to have a second precision type different in precision than the first precision type to thereby generate at least one modified data value. The at least one modified data value is stored in at least one vector element of the plurality of vector elements. An alignment of the at least one modified data value is determined relative to a boundary of a vector element of the vector register. An alignment operation to re-align the at least one modified data value based on the boundary of the vector element of the vector register is performed.
    Type: Grant
    Filed: October 14, 2008
    Date of Patent: January 4, 2011
    Assignee: International Business Machines Corporation
    Inventors: Alexandre E. Eichenberger, Bruce M. Fleischer, Michael K. Gschwind
  • Automated Critical Area Allocation in a Physical Synthesized Hierarchical Design
    Publication number: 20100218155
    Abstract: A method, computer program product, and data processing system for efficiently performing automated placement of timing-critical unit-level cells in a hierarchical integrated circuit design is disclosed. In preparation for global optimization the entire unit at the cell level, macro-level cells are assigned a “placement force” that serves to limit the movement of the macro-level cells from their current position. Movement boundaries for each macro element are also defined, so as to keep the components in a given macro element in relative proximity to each other. Optimization/placement of the unit design is then performed, via a force-directed layout algorithm, on a “flattened” model of the design while respecting the movement boundaries. Following this “flattened” optimization, the placed “unit-level” cells are modeled as blockages and the macro elements are optimized individually, while respecting the location(s) of the blockages.
    Type: Application
    Filed: February 26, 2009
    Publication date: August 26, 2010
    Inventors: Bruce M. Fleischer, David J. Geiger, Hung C. Ngo, Ruchir Puri, Hoaxing Ren
  • Systems, methods and computer program products for providing a combined moduli-9 and 3 residue generator
    Patent number: 7739323
    Abstract: Systems, methods and computer program products for providing a combined moduli-9 and 3 residue generator. The methods include receiving a number in binary coded decimal (BCD) or binary format. A modulus-9 residue of the number is calculated. The modulus-9 residue that is calculated includes a modulus-3 residue of the number. The modulus-3 residue of the number is output. If the number is in BCD format, then the modulus-9 residue of the number is output.
    Type: Grant
    Filed: June 20, 2006
    Date of Patent: June 15, 2010
    Assignee: International Business Machines Corporation
    Inventors: Daniel Lipetz, Bruce M. Fleischer, Eric M. Schwarz
  • System and method for a floating point unit with feedback prior to normalization and rounding
    Patent number: 7730117
    Abstract: A system for performing floating point arithmetic operations including an input register adapted for receiving an operand. The system also includes a mechanism for performing a shift or masking operation in response to determining that the operand is in an un-normalized format. The system also includes instructions for performing single precision incrementing of the operand in response to determining that the operand is single precision, that the operand requires the incrementing based on the results of a previous operation and that the previous operation did not perform the incrementing. The operand was created in the previous operation. The system further includes instructions for performing double precision incrementing of the operand in response to determining that the operand is double precision, that the operand requires the incrementing based on the results of the previous operation and that the previous operation did not perform the incrementing.
    Type: Grant
    Filed: February 9, 2005
    Date of Patent: June 1, 2010
    Assignee: International Business Machines Corporation
    Inventors: Bruce M. Fleischer, Juergen Haess, Michael Kroener, Martin S. Schmookler, Eric M. Schwarz, Son Dao-Trong
  • Scheme to optimize scan chain ordering in designs
    Patent number: 7721171
    Abstract: A method for optimizing a scan chain ordering in circuit designs in an electronic computer-aided design system is provided.
    Type: Grant
    Filed: August 16, 2007
    Date of Patent: May 18, 2010
    Assignee: International Business Machines Corporation
    Inventors: Mark A. Erle, Bruce M. Fleischer, Daniel Lipetz
  • Dynamically Aligning Enhanced Precision Vectors Based on Addresses Corresponding to Reduced Precision Vectors
    Publication number: 20100095086
    Abstract: Mechanisms for aligning enhanced precision vectors based on reduced precision data values are provided. At least one data value, having a first precision type, is received for storing in a vector register. The vector register stores data as a vector having a plurality of vector elements. The first precision type is modified to have a second precision type different in precision than the first precision type to thereby generate at least one modified data value. The at least one modified data value is stored in at least one vector element of the plurality of vector elements. An alignment of the at least one modified data value is determined relative to a boundary of a vector element of the vector register. An alignment operation to re-align the at least one modified data value based on the boundary of the vector element of the vector register is performed.
    Type: Application
    Filed: October 14, 2008
    Publication date: April 15, 2010
    Applicant: International Business Machines Corporation
    Inventors: Alexandre E. Eichenberger, Bruce M. Fleischer, Michael K. Gschwind
  • Dynamic Data Driven Alignment and Data Formatting in a Floating-Point SIMD Architecture
    Publication number: 20100095087
    Abstract: Mechanisms are provided for dynamic data driven alignment and data formatting in a floating point SIMD architecture. At least two operand inputs are input to a permute unit of a processor. Each operand input contains at least one floating point value upon which a permute operation is to be performed by the permute unit. A control vector input, having a plurality of floating point values that together constitute the control vector input, is input to the permute unit of the processor for controlling the permute operation of the permute unit. The permute unit performs a permute operation on the at least two operand inputs according to a permutation pattern specified by the plurality of floating point values that constitute the control vector input. Moreover, a result output of the permute operation is output from the permute unit to a result vector register of the processor.
    Type: Application
    Filed: October 14, 2008
    Publication date: April 15, 2010
    Applicant: International Business Machines Corporation
    Inventors: Alexandre E. Eichenberger, Bruce M. Fleischer, Michael K. Gschwind
  • System and method for performing decimal to binary conversion
    Patent number: 7660838
    Abstract: A method for converting from decimal to binary including receiving a binary coded decimal (BCD) number made up of one or more sets of three digits. A running sum and a running carry are set to zero. A process is performed for each set of three digits in the BCD number in order from the set of three digits containing the three most significant digits of the BCD number to the digits containing the three least significant digits of the BCD number. The process includes: creating six partial products based on the set of three digits, the running sum and the running carry; combining the six partial products into two partial products; and storing the two partial products in the running sum and the running carry. The running sum and the running carry from each set of three digits are combined into a final binary result.
    Type: Grant
    Filed: February 9, 2005
    Date of Patent: February 9, 2010
    Assignee: International Business Machines Corporation
    Inventors: Steven R. Carlough, Bruce M. Fleischer, Wen H. Li, Eric M. Schwarz
  • Method and System for a Wiring-Efficient Permute Unit
    Publication number: 20090177870
    Abstract: A method of providing wiring efficiency in a permute unit. Multiple selectors receive input data and shared control signals from multiple register files. The permute unit includes multiple multiplexors (MUXs) coupled to multiple logical AND gates. The multiple logical AND gates are coupled to multiple logical OR gates. The logical AND gates are physically separated from the logical OR gates. The logical AND gates receive input from one or more output data signals from the selectors. The logical OR gates combine the one or more output signals from the logical AND gates and provide output data from the permute unit.
    Type: Application
    Filed: January 3, 2008
    Publication date: July 9, 2009
    Inventors: Bruce M. Fleischer, Hung C. Ngo, Jun Sawada
  • SCHEME TO OPTIMIZE SCAN CHAIN ORDERING IN DESIGNS
    Publication number: 20090049353
    Abstract: A method for optimizing a scan chain ordering in circuit designs in an electronic computer-aided design system is provided.
    Type: Application
    Filed: August 16, 2007
    Publication date: February 19, 2009
    Applicant: International Business Machines Corporation
    Inventors: Mark A. Erle, Bruce M. Fleischer, Daniel Lipetz
  • SYSTEMS, METHODS AND COMPUTER PROGRAM PRODUCTS FOR PROVIDING A COMBINED MODULI-9 AND 3 RESIDUE GENERATOR
    Publication number: 20070294330
    Abstract: Systems, methods and computer program products for providing a combined moduli-9 and 3 residue generator. The methods include receiving a number in binary coded decimal (BCD) or binary format. A modulus-9 residue of the number is calculated. The modulus-9 residue that is calculated includes a modulus-3 residue of the number. The modulis-3 residue of the number is output. If the number is in BCD format, then the modulus-9 residue of the number is output.
    Type: Application
    Filed: June 20, 2006
    Publication date: December 20, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Daniel Lipetz, Bruce M. Fleischer, Eric M. Schwarz
  • Processor design for extended-precision arithmetic
    Patent number: 6842765
    Abstract: A processor for performing a multiply-add instruction on a multiplicand A, a multiplier B, and an addend C, to calculate a result D. The operands are double-precision floating point numbers and the result D is a canonical-form extended-precision floating point number having a high order component and a low order component. The processor is a fused multiply-add processor with a multiplier, an adder, a normalizer and a rounder. The post-adder data path, the normalizer and the rounder each have a data width sufficient to represent post-adder intermediate results to permit the high and low order words of a correctly-rounded result D to be computed. The mantissas of the extended-precision result D are provided such that the high order word mantissa is stored to double precision registers.
    Type: Grant
    Filed: July 31, 2001
    Date of Patent: January 11, 2005
    Assignee: International Business Machines Corporation
    Inventors: Robert F. Enenkel, Fred G. Gustavson, Bruce M. Fleischer, Jose E. Moreira
  • Processor design for extended-precision arithmetic
    Publication number: 20020107900
    Abstract: A processor for performing a multiply-add instruction on a multiplicand A, a multiplier B, and an addend C, to calculate a result D. The operands are double-precision floating point numbers and the result D is a canonical-form extended-precision floating point number having a high order component and a low order component. The processor is a fused multiply-add processor with a multiplier, an adder, a normalizer and a rounder. The post-adder data path, the normalizer and the rounder each have a data width sufficient to represent post-adder intermediate results to permit the high and low order words of a correctly-rounded result D to be computed. The mantissas of the extended-precision result D are provided such that the high order word mantissa is stored to double precision registers.
    Type: Application
    Filed: July 31, 2001
    Publication date: August 8, 2002
    Applicant: International Business Machines Corporation
    Inventors: Robert F. Enenkel, Fred G. Gustavson, Bruce M. Fleischer, Jose E. Moreira
  • Self-resetting CMOS parallel adder with a bubble pipelined architecture, tri-rail merging logic, and enhanced testability
    Patent number: 5633820
    Abstract: A parallel self-resetting parallel binary adder provides high speed addition and subtraction. The adder combines the advantages of a fully custom design methodology with the higher performance potential of self-resetting complementary metal oxide semiconductor (CMOS) circuits. The adder logic architecture is carry look-ahead with two bit groups and requires six rows of merge logic to calculate the carry out of the Most Significant Bit (MSB). Loading on the critical path of the adder is reduced by moving as many merge blocks as possible to later rows. This allows the fan-out per stage in the critical path to be reduced from around three to two or less. The adder utilizes a bubble pipelined circuit architecture. For the adder, a bubble pipe segment consists of a row of self-resetting circuit blocks.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: May 27, 1997
    Assignee: International Business Machines Corporation
    Inventors: Michael P. Beakes, Barbara A. Chappell, Terry I. Chappell, Bruce M. Fleischer, Thao N. Nguyen
  • Fast comparator circuit
    Patent number: 5471188
    Abstract: A fast comparator circuit, including a plurality of first switches operating in parallel. A first data bit from a first data word is input into a first input of each first switch, and a corresponding second data bit from a second data word is respectively input into a second input of each first switch. Each first switch provides a first logic state output when the first data bit matches the corresponding second data bit or a second logic state output when the first data bit does not match the second data bit. A plurality of second switches receive the respective logic state outputs and produce a combined output, indicating an all match or a mismatch, to a third switch combination connected to a first branch node and a second branch node to create a first voltage difference between the first and second branch nodes when an all match output results and a second voltage difference between the first and second branch node when a mismatch output results.
    Type: Grant
    Filed: October 7, 1994
    Date of Patent: November 28, 1995
    Assignee: International Business Machines Corporation
    Inventors: Barbara A. Chappell, Terry I. Chappell, Bruce M. Fleischer, Stanley E. Schuster